T. Sansaloni

Publication Activity (10 Years)

Years Active: 1999-2009
Publications (10 Years): 0

Publications

Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56 (1) (2009)
A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J. Signal Process. Syst. 56 (1) (2009)
Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. J. Signal Process. Syst. 52 (1) (2008)
Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. J. Signal Process. Syst. 52 (2) (2008)
A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls
Design of an efficient digital down-converter for a SDR-based DVB-S receiver. ECCTD (2007)
T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47 (2) (2007)
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
Design of high performance timing recovery loops for communication applications. SiPS (2006)
Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL (2005)
T. Sansaloni, Javier Valls, Keshab K. Parhi
Digit-Serial Complex-Number Multipliers on FPGAs. J. VLSI Signal Process. 33 (1-2) (2003)
A. Perez-Pascual, T. Sansaloni, Javier Valls
FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) (2002)
A. Perez-Pascual, T. Sansaloni, Javier Valls
FPGA based on-line complex-number multipliers. ICECS (2001)
T. Sansaloni, A. Perez-Pascual, Javier Valls
Distributed arithmetic radix-2 butterflies for FPGA. ICECS (2001)
Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS (1999)