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A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation.
Marcos Martínez-Peiró
Javier Valls
T. Sansaloni
A. Perez-Pascual
Eduardo I. Boemo
Published in:
ICECS (1999)
Keyphrases
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fir filters
hardware implementation
hardware architecture
vlsi implementation
xilinx virtex
signal processing
image processing
multiscale
efficient implementation
filter design
finite impulse response
fpga device