Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.
Vicente Torres-CarotAsuncion Perez-PascualTrinidad SansaloniJavier VallsPublished in: ICECS (2012)
Keyphrases
- ldpc codes
- low density parity check
- parallel hardware
- decoding algorithm
- error correction
- turbo codes
- message passing
- shared memory
- distributed video coding
- channel coding
- reed solomon
- fpga implementation
- distributed source coding
- field programmable gate array
- parallel architecture
- error control
- parallel computing
- low complexity
- parallel processing
- pipelined architecture
- source code
- error resilience
- distributed memory
- hardware implementation
- rate allocation
- compressive sensing
- signal processing
- lookup table
- unequal error protection
- hardware design
- massively parallel
- error concealment
- image quality