Eduardo R. de Lima

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 7

Top Topics

Hardware Architecture

Fpga Implementation

Pipelined Architecture

Tensor Decomposition

Top Venues

Publications

Raphael R. N. Souza, Agord M. Pinto, Roberto Lacerda de Orio, Leandro Tiago Manera, Eduardo R. de Lima
A 2.0 GHz LC- VCO with 1.4 GHz Tuning Range and Switched Varactor Array. LASCAS (2024)
Raphael R. N. Souza, Agord M. P. Júnior, Hercílio M. Cavalcanti, Eduardo R. de Lima, Leandro Tiago Manera
Microelectronics Education Environment: A Training Model for the Semiconductors Market. EDUCON (2021)
Denise C. Alves-Tamagno, Eduardo R. de Lima, Renato R. Lopes
A Low Complexity ICFO Estimator and Compensator for IEEE 802.15.4g MR-OFDM PHY: Algorithm Proposal and Hardware Implementation. PIMRC (2018)
Vanessa B. Olivatto, Renato R. Lopes, Eduardo R. de Lima
Simplified Method for Log-Likelihood Ratio Approximation in High-Order Modulations Based on the Voronoi Decomposition. IEEE Trans. Broadcast. 63 (3) (2017)
Denise C. Alves, Gabriel S. da Silva, Eduardo R. de Lima, Cesar G. Chaves, Daniel Urdaneta, Tiago D. Perez, Maique C. Garcia
Architecture design and implementation of key components of an OFDM transceiver for IEEE 802.15.4g. ISCAS (2016)
Gabriel S. da Silva, Eduardo R. de Lima, Cesar G. Chaves
Using maximal ratio combining and subcarrier selection to improve the OFDM receiver performance in IEEE802.15.4g. PIMRC (2016)
José A. Bianco Filho, Cesar G. Chaves, Eduardo R. de Lima, Luís Geraldo P. Meloni
Algorithm and Digital Circuit for Blind Frequency and Band Estimation in Spans with Multiple Signals. GLOBECOM (2016)
Denise C. Alves, Eduardo R. de Lima
A frame synchronizer for IEEE 802.15.4-g MR-OFDM PHY: Algorithm proposal and hardware implementation. LATINCOM (2015)
Augusto F. R. Queiroz, Gabriel S. da Silva, Cesar G. Chaves, Tiago D. Perez, Daniel G. Urdanetta, Denise C. Alves, Maique C. Garcia, Eduardo R. de Lima
Demo: FPGA implementation of an IEEE802.15.4g MR-OFDM baseband modem for smart metering utility networks. GCCE (2015)
Gabriel S. da Silva, Augusto F. R. Queiroz, Eduardo R. de Lima, Cesar G. Chaves
A novel fine frequency estimation serial architecture applied in satellite communications. ISCAS (2015)
Jessica A. J. de Oliveira, Augusto F. R. Queiroz, Eduardo R. de Lima, Jacqueline Gomes Mertes
An MR-FSK transceiver compliant to IEEE802.15.4g for smart metering utility applications: FPGA implementation and ASIC resource estimation. LATINCOM (2015)
Eduardo R. de Lima, Augusto F. R. Queiroz, Denise C. Alves, Gabriel S. da Silva, Cesar G. Chaves, Jacqueline Gomes Mertes, Thiago M. Marson
A detailed DVB-S2 receiver implementation: FPGA prototyping and preliminary ASIC resource estimation. LATINCOM (2014)
Andre N. Sapper, Eduardo R. de Lima, Cesar G. Chaves, Gabriel S. da Silva, Augusto F. R. Queiroz, Marcelo A. C. Fernandes
An adaptive equalizer for reliable transmissions in DVB-S2 satellite communications under ISI. LATINCOM (2014)
Eduardo R. de Lima, Santiago J. Flores, Vicenc Almenar-Terre, Ma José Canet
Analysis and Contrast Between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation. ICT (2004)
Eduardo R. de Lima, Santiago J. Flores, Vicenç Almenar, Amparo Girona
Performance enhancements in OFDM-WLAN systems using MIMO access techniques. ISWCS (2004)
Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC (2004)
Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima
Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. FPL (2004)
Eduardo R. de Lima, Santiago J. Flores, Vicenc Almenar-Terre, Ma José Canet
Analysis and Contrast Between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation. SAPIR (2004)