Francisco Garcia-Herrero

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 24

Top Topics

Message Exchange

Decoding Algorithm

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Circuits Syst. Signal Process.

Publications

José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. 59 (5) (2023)
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
Layered Decoding of Quantum LDPC Codes. ISTC (2023)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers 72 (3) (2023)
Sana Javed, Francisco Garcia-Herrero, Bane Vasic, Mark F. Flanagan
Low-Complexity Linear Programming Based Decoding of Quantum LDPC codes. CoRR (2023)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián, Oscar Ruano, Francisco Garcia-Herrero
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. J. Supercomput. 78 (6) (2022)
Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. 99 (2022)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Javier Valls, Francisco Garcia-Herrero, Nithin Raveendran, Bane Vasic
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. IEEE Access 9 (2021)
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 21 (4) (2021)
Francisco Garcia-Herrero, Gary McGuire, Mark F. Flanagan, Alfonso Sánchez-Macián, Juan Antonio Maestro
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
David Villanueva Valentín-Gamazo, Neslon Tuesta Durango, Francisco Garcia-Herrero, M. Isabel Mansilla Blanco, M. Cruz Rey de las Moras
Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture. CINAIC (2021)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Low delay non-binary error correction codes based on Orthogonal Latin Squares. Integr. 76 (2021)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access 9 (2021)
Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. IEEE Access 8 (2020)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase. IEEE Trans. Circuits Syst. (12) (2020)
Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero, Juan Antonio Maestro
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA. Circuits Syst. Signal Process. 39 (11) (2020)
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Garcia-Herrero
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. Circuits Syst. Signal Process. 38 (4) (2019)
J. M. Català-Pérez, Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls, David Declercq
Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. Circuits Syst. Signal Process. 38 (11) (2019)
Vicente Torres, Javier Valls, María José Canet, Francisco Garcia-Herrero
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). NEWCAS (2018)
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
High-Performance NB-LDPC Decoder With Reduction of Message Exchange. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Jesus Omar Lacruz, Francisco Garcia-Herrero, David Declercq, Javier Valls
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual
A 630 Mbps non-binary LDPC decoder for FPGA. ISCAS (2015)
Francisco Garcia-Herrero, David Declercq, Javier Valls
Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. IEEE Commun. Lett. 18 (5) (2014)
Francisco Garcia-Herrero, David Declercq, Javier Valls
A symbol flipping decoder for NB-LDPC relying on multiple votes. ISTC (2014)
J. M. Català-Pérez, Francisco Garcia-Herrero, Javier Valls, K. Liu, S. Lin
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. IEEE Commun. Lett. 18 (12) (2014)
Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls
Low latency T-EMS decoder for non-binary LDPC codes. ACSSC (2013)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. Circuits Syst. Signal Process. 32 (2) (2013)
Francisco Garcia-Herrero, Ma José Canet, Javier Valls
High-speed NB-LDPC decoder for wireless applications. ISPACS (2013)
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls, Mark F. Flanagan
Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. IEEE Commun. Lett. 16 (6) (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls
Decoder for an enhanced serial generalized bit flipping algorithm. ICECS (2012)
Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher
High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits Syst. Signal Process. 30 (6) (2011)