Juan Antonio Maestro

ORCID

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 58

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Microelectron. Reliab.

IEEE Trans. Computers

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. 59 (5) (2023)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers 72 (3) (2023)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. 99 (2022)
Kyle W. Gear, Alfonso Sánchez-Macián, Juan Antonio Maestro
An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique. Microprocess. Microsystems 90 (2022)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 21 (4) (2021)
Francisco Garcia-Herrero, Gary McGuire, Mark F. Flanagan, Alfonso Sánchez-Macián, Juan Antonio Maestro
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Low delay non-binary error correction codes based on Orthogonal Latin Squares. Integr. 76 (2021)
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access 9 (2021)
Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. IEEE Access 8 (2020)
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes. DCIS (2020)
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase. IEEE Trans. Circuits Syst. (12) (2020)
Imran Wali, Alfonso Sánchez-Macián, Alexis Ramos, Juan Antonio Maestro
Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. ICECS (2020)
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro
Toward a Fault-Tolerant Star Tracker for Small Satellite Applications. IEEE Trans. Aerosp. Electron. Syst. 56 (5) (2020)
Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero, Juan Antonio Maestro
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA. Circuits Syst. Signal Process. 39 (11) (2020)
Alexis Ramos, Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro
An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs. IEEE Trans. Computers 68 (9) (2019)
Luis Alberto Aranda, Pedro Reviriego, Ricardo Gonzalez-Toral, Juan Antonio Maestro
Protection Scheme for Star Tracker Images. IEEE Trans. Aerosp. Electron. Syst. 55 (1) (2019)
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs. IEEE Access 7 (2019)
Alfonso Sánchez-Macián, Luis Alberto Aranda, Pedro Reviriego, Vahdaneh Kiani, Juan Antonio Maestro
Enhancing Instruction TLB Resilience to Soft Errors. IEEE Trans. Computers 68 (2) (2019)
Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego, Juan Antonio Maestro
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Ana Cóbreces, Alberto Regadío, Jesús Tabero, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
Seu and Sefi error detection and correction on a ddr3 memory system. Microelectron. Reliab. 91 (2018)
Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Trans. Computers 67 (2) (2018)
Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro, Zhen Gao
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs. IEEE Trans. Computers 67 (7) (2018)
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Ricardo Gonzalez-Toral, Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2018)
Jesús Tabero, Alberto Regadío, César Pérez, Jesús Pazos, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
Modular fault tolerant processor architecture on a SoC for space. Microelectron. Reliab. 83 (2018)
Zhen Gao, Ming Zhou, Pedro Reviriego, Juan Antonio Maestro
Efficient Fault-Tolerant Design for Parallel Matched Filters. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. Microelectron. Reliab. 81 (2018)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
A method to protect Cuckoo filters from soft errors. Microelectron. Reliab. 72 (2017)
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro, Shanshan Liu
Single Event Transient Tolerant Bloom Filter Implementations. IEEE Trans. Computers 66 (10) (2017)
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes. IEEE Trans. Reliab. 66 (2) (2017)
Shanshan Liu, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro, Liyi Xiao
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016). Microelectron. Reliab. 69 (2017)
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
Combined Modular Key and Data Error Protection for Content-Addressable Memories. IEEE Trans. Computers 66 (6) (2017)
Alexis Ramos, Juan Antonio Maestro, Pedro Reviriego
Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. Microelectron. Reliab. 78 (2017)
Jorge A. Martínez, Juan Antonio Maestro, Pedro Reviriego
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. IEEE Comput. Archit. Lett. 16 (2) (2017)
Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio Maestro
A method to recover critical bits under a double error in SEC-DED protected memories. Microelectron. Reliab. 73 (2017)
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. Microelectron. Reliab. 56 (2016)
Pedro Reviriego, Mustafa Demirci, Adrian Evans, Juan Antonio Maestro
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits. IEEE Trans. Circuits Syst. II Express Briefs (2) (2016)
Zhen Gao, Pedro Reviriego, Juan Antonio Maestro
Efficient fault tolerant parallel matrix-vector multiplications. IOLTS (2016)
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
Improving counting Bloom filter performance with fingerprints. Inf. Process. Lett. 116 (4) (2016)
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes. IEEE Trans. Computers 65 (9) (2016)
Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, Juan Antonio Maestro
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Pedro Reviriego, Mustafa Demirci, Jesús Tabero, Alberto Regadío, Juan Antonio Maestro
DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs. Microelectron. Reliab. 63 (2016)
Pedro Reviriego, Kenneth J. Christensen, Juan Antonio Maestro
A Comment on "Fast Bloom Filters and Their Generalization". IEEE Trans. Parallel Distributed Syst. 27 (1) (2016)
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
Optimizing the Implementation of SEC-DAEC Codes in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput. IEEE Trans. Computers 65 (1) (2016)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
A method to protect Bloom filters from soft errors. DFTS (2015)
Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Jing Wang, Juan Antonio Maestro
Efficient Coding Schemes for Fault-Tolerant Parallel Filters. IEEE Trans. Circuits Syst. II Express Briefs (7) (2015)
Pedro Reviriego, Salvatore Pontarelli, Adrian Evans, Juan Antonio Maestro
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro
Fault Tolerant Parallel Filters Based on Error Correction Codes. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Luis J. Saiz-Adalid, Pedro Reviriego, Pedro J. Gil, Salvatore Pontarelli, Juan Antonio Maestro
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Salvatore Pontarelli, Pedro Reviriego, Marco Ottavi, Juan Antonio Maestro
Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes. IEEE Trans. Computers 64 (5) (2015)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
A Synergetic Use of Bloom Filters for Error Detection and Correction. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Pedro Reviriego, Serdar Zafer Can, Çagri Eryilmaz, Juan Antonio Maestro, Oguz Ergin
Exploiting processor features to implement error detection in reduced precision matrix multiplications. Microprocess. Microsystems 38 (6) (2014)
Vijay Sivaraman, Pedro Reviriego, Zhi Zhao, Alfonso Sánchez-Macián, Arun Vishwanath, Juan Antonio Maestro, Craig Russell
An experimental power profile of Energy Efficient Ethernet switches. Comput. Commun. 50 (2014)
Pedro Reviriego, Salvatore Pontarelli, Alfonso Sánchez-Macián, Juan Antonio Maestro
A Method to Extend Orthogonal Latin Square Codes. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Zhen Gao, Pedro Reviriego, X. Li, Juan Antonio Maestro, Ming Zhao, J. Wang
A fault tolerant implementation of the Goertzel algorithm. Microelectron. Reliab. 54 (1) (2014)
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
Optimized parallel decoding of difference set codes for high speed memories. Microelectron. Reliab. 54 (11) (2014)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
Efficient implementation of error correction codes in hash tables. Microelectron. Reliab. 54 (1) (2014)
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
Efficient Flow Sampling With Back-Annotated Cuckoo Hashing. IEEE Commun. Lett. 18 (10) (2014)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing. IEEE Commun. Lett. 18 (5) (2014)
Pedro Reviriego, Oscar Ruano, Mark F. Flanagan, Salvatore Pontarelli, Juan Antonio Maestro
An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. IEEE Trans. Circuits Syst. II Express Briefs (8) (2013)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication. Microprocess. Microsystems 37 (8-D) (2013)
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction. IEEE Des. Test 30 (2) (2013)
Salvatore Pontarelli, Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
Low Complexity Concurrent Error Detection for Complex Multiplication. IEEE Trans. Computers 62 (9) (2013)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro
Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design. IEEE Trans. Circuits Syst. II Express Briefs (8) (2013)
Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. DFTS (2013)
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories. IEEE Trans. Circuits Syst. II Express Briefs (7) (2013)
Costas Argyrides, Pedro Reviriego, Juan Antonio Maestro
Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors. IEEE Trans. Reliab. 62 (1) (2013)
Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, Juan Antonio Maestro
Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values. IEEE Comput. Archit. Lett. 12 (1) (2013)
Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
Low Power embedded DRAM caches using BCH code partitioning. IOLTS (2012)
Pedro Reviriego, Oscar Ruano, Juan Antonio Maestro
Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)
Pedro Reviriego, Mark F. Flanagan, Shih-Fu Liu, Juan Antonio Maestro
Multiple Cell Upset Correction in Memories Using Difference Set Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2012)
Pedro Reviriego, Costas Argyrides, Juan Antonio Maestro
Efficient error detection in Double Error Correction BCH codes for memory applications. Microelectron. Reliab. 52 (7) (2012)
José Luis García-Dorado, Eduardo Magaña, Pedro Reviriego, Mikel Izal, Daniel Morató, Juan Antonio Maestro, Javier Aracil, Jorge E. López de Vergara
Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network. J. Supercomput. 62 (3) (2012)
Pedro Reviriego, Vijay Sivaraman, Zhi Zhao, Juan Antonio Maestro, Arun Vishwanath, Alfonso Sánchez-Macián, Craig Russell
An energy consumption model for Energy Efficient Ethernet switches. HPCS (2012)
Pedro Reviriego, Juan Antonio Maestro, José Alberto Hernández, David Larrabeiti
Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate. Trans. Emerg. Telecommun. Technol. 23 (3) (2012)
Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Pedro Reviriego, Lars Holst, Juan Antonio Maestro
On the expected longest length probe sequence for hashing with separate chaining. J. Discrete Algorithms 9 (3) (2011)
Pedro Reviriego, Shanshan Liu, Juan Antonio Maestro
Mitigation of permanent faults in adaptive equalizers. Microelectron. Reliab. 51 (3) (2011)
Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg
Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. DAC (2011)
Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley
Implications of energy efficient Ethernet for hubs and switches. Int. J. Commun. Networks Distributed Syst. 6 (1) (2011)
Pedro Reviriego, Ken Christensen, Alfonso Sánchez-Macián, Juan Antonio Maestro
Using Coordinated Transmission with Energy Efficient Ethernet. Networking (1) (2011)
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
A fast and efficient technique to apply Selective TMR through optimization. Microelectron. Reliab. 51 (12) (2011)
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
Validation and optimization of TMR protections for circuits in radiation environments. DDECS (2011)
Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong
Mitigating the effects of large multiple cell upsets (MCUs) in memories. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
David Larrabeiti, Pedro Reviriego, José Alberto Hernández, Juan Antonio Maestro, Manuel Urueña
Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability. Opt. Switch. Netw. 8 (3) (2011)
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan
Fault Tolerant Single Error Correction Encoders. J. Electron. Test. 27 (2) (2011)
Pedro Reviriego, Ken Christensen, Juan Rabanillo, Juan Antonio Maestro
An Initial Evaluation of Energy Efficient Ethernet. IEEE Commun. Lett. 15 (5) (2011)
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro, Anne O'Donnell
Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution. IEEE Trans. Computers 60 (10) (2011)
Chris J. Bleakley, Pedro Reviriego, Juan Antonio Maestro
Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms. Microelectron. Reliab. 51 (6) (2011)

Juan Antonio Maestro.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Juan Antonio Maestro