Anees Ullah

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 25

Top Topics

Field Programmable Gate Array

Fpga Implementation

Direction Of Arrival

Fault Tolerance

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Computers

IEEE Embed. Syst. Lett.

Publications

Shahid Ullah, Yingmei Li, Wajeeha Rahman, Farhan Ullah, Muhammad Ijaz, Anees Ullah, Gulzar Ahmad, Hameed Ullah, Tianshun Gao
CO-19 PDB 2.0: A Comprehensive COVID-19 Database with Global Auto-Alerts, Statistical Analysis, and Cancer Correlations. Database J. Biol. Databases Curation 2024 (2024)
Achref Rebai, Mubarak Adetunji Ojewale, Anees Ullah, Marco Canini, Suhaib A. Fahmy
SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning. NAIC (2024)
Zhen Gao, Yinghao Cheng, Qiang Liu, Anees Ullah, Pedro Reviriego
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Muhammad Awais, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs. ACM Trans. Embed. Comput. Syst. 22 (4) (2023)
Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, Fabrizio Lombardi
Error-Resilient Data Compression With Tunstall Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Shahid Ullah, Wajeeha Rahman, Farhan Ullah, Anees Ullah, Gulzar Ahmad, Muhammad Ijaz, Hameed Ullah, Zilong Zheng, Tianshun Gao
AVPCD: a plant-derived medicine database of antiviral phytochemicals for cancer, Covid-19, malaria and HIV. Database J. Biol. Databases Curation 2023 (2023)
Zhen Gao, Jinchang Shi, Qiang Liu, Anees Ullah, Pedro Reviriego
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Zhen Gao, Jiajun Xiao, Qiang Liu, Anees Ullah, Pedro Reviriego
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Zhen Gao, Han Zhang, Yi Yao, Jiajun Xiao, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning. IEEE Trans. Very Large Scale Integr. Syst. 30 (3) (2022)
Zhen Gao, Jinhua Zhu, Tong Yan Tyan, Anees Ullah, Pedro Reviriego
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Ali Zahir, Anees Ullah, Pedro Reviriego, Syed Riaz Ul Hassnain
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs. IEEE Embed. Syst. Lett. 14 (1) (2022)
Uzma M. Butt, Shoab A. Khan, Anees Ullah, Abdul Khaliq, Pedro Reviriego, Ali Zahir
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Youcef Belkhier, Abdelyazid Achour, Nasim Ullah, Rabindra N. Shaw, Zaheer Farooq, Anees Ullah, Ali Nasser Alzaed
Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System. IEEE Access 9 (2021)
Zhen Gao, Lingling Zhang, Yinghao Cheng, Kangkang Guo, Anees Ullah, Pedro Reviriego
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Anees Ullah, Pedro Reviriego, Adeel Akram, Malik Najmus Siraj
Switch-Based High Cardinality Node Detection. IEEE Embed. Syst. Lett. 13 (4) (2021)
Anees Ullah, Salvatore Pontarelli, Pedro Reviriego
FlexTCAM: Beyond Memory Based TCAM Emulation on FPGAs. NFV-SDN (2020)
Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28 (12) (2020)
Pedro Reviriego, Anees Ullah, Salvatore Pontarelli
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Pedro Reviriego, Salvatore Pontarelli, Anees Ullah
Error Detection and Correction in SRAM Emulated TCAMs. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Trans. Computers 67 (2) (2018)
Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir, Giuseppe Bianchi
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays. HPSR (2018)
Nasim Ullah, Anees Ullah, Asier Ibeas, Jorge A. Herrera
Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems. IEEE Access 5 (2017)
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers 66 (6) (2017)
Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. J. Syst. Archit. 81 (2017)
Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andres Cardona, Carles Ferrer
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectron. Reliab. 75 (2017)
Anees Ullah, Luca Sterpone
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. J. Electron. Test. 30 (4) (2014)
Ernesto Sánchez, Luca Sterpone, Anees Ullah
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. FPL (2014)
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
An error-detection and self-repairing method for dynamically and partially reconfigurable systems. ETS (2013)
Luca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. AHS (2013)
Luca Sterpone, Anees Ullah
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs. AHS (2013)
Sadaqat ur Rehman, Muhammad Bilal, Basharat Ahmad, Khawaja Muhammad Yahya, Anees Ullah, Obaid Ur Rehman
Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN). CoRR (2012)