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Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
Pedro Reviriego
Salvatore Pontarelli
Anees Ullah
Ali Zahir
Giuseppe Bianchi
Published in:
HPSR (2018)
Keyphrases
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hardware design
embedded systems
field programmable gate array
hardware architecture
case study
design process
image processing algorithms
fpga technology
neural network
image processing
general purpose
low cost
computing systems
massively parallel
parallel architectures
application specific integrated circuits