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A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
Zhen Gao
Jiajun Xiao
Qiang Liu
Anees Ullah
Pedro Reviriego
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2023)
Keyphrases
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fault tolerant
fault tolerance
design methodology
load balancing
distributed systems
high availability
high assurance
parallel processing
safety critical
parallel computing
evolvable hardware