Luca Sterpone

ORCID

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 96

Top Venues

IOLTS

Microelectron. Reliab.

ETS

Publications

Eleonora Vacca, Giorgio Cora, Sarah Azimi, Luca Sterpone
Assessment of RISC-V Processor Suitability for Satellite Applications. CF (Companion) (2024)
Luca Sterpone, Sarah Azimi, Corrado De Sio
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Rosario Milazzo, Vincenzo De Marco, Corrado De Sio, Sophie M. Fosson, Lia Morra, Luca Sterpone
On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks. DDECS (2024)
Giorgio Cora, Corrado De Sio, Daniele Rizzieri, Sarah Azimi, Luca Sterpone
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems. DDECS (2024)
Giorgio Cora, Corrado De Sio, Sarah Azimi, Luca Sterpone
A Novel Robust Core for Detecting Node Failures in FPGA Clusters. CF (2024)
Corrado De Sio, Andrea Avignone, Luca Sterpone, Silvia Chiusano
Scalable K-Nearest Neighbors Implementation using Distributed Embedded Systems. CF (2024)
Daniele Rizzieri, Sarah Azimi, Luca Sterpone, Corrado De Sio, Thomas Borel, Viyas Gupta, Margherita Cardi
Programmable SEL Test Monitoring System for Radiation Hardness Assurance. DSN-S (2023)
Corrado De Sio, Luca Sterpone, Sarah Azimi
Reliability Analysis of Microarchitectural Faults in GPGPU-based HPC Systems. CF (2023)
Andrea Portaluri, Corrado De Sio, Luca Sterpone
Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset. CF (2023)
Eleonora Vacca, Sarah Azimi, Luca Sterpone
A Comprehensive Analysis of Transient Errors on Systolic Arrays. DDECS (2023)
Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs, Filomena Decuzzi
PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs. SMACD (2023)
Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs, Stephen King
EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications. DATE (2023)
Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, J. Guerrero, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, J. Aribido, Jyotika Athavale
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections. DATE (2023)
Andrea Portaluri, Sarah Azimi, Luca Sterpone
Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs. ISPDC (2023)
Eleonora Vacca, Giorgio Ajmone, Luca Sterpone
RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators. ICCD (2023)
Sarah Azimi, Corrado De Sio, Francesco Carlucci, Luca Sterpone
Fighting for a future free from violence: A framework for real-time detection of "Signal for Help". Intell. Syst. Appl. 17 (2023)
Corrado De Sio, Luca Sterpone
High-Performance SET Hardening Technique for Vision-Oriented Applications. SMACD (2023)
Sarah Azimi, Corrado De Sio, Luca Sterpone
Enhanced Video Surveillance Systems for "Signal for Help" Detection on Edge Devices. ISTAS (2023)
Luca Sterpone, Sarah Azimi, Corrado De Sio
A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace. CF (2023)
Andrea Portaluri, Sarah Azimi, Corrado De Sio, Daniele Rizzieri, Luca Sterpone
On the Reliability of Real-Time Operating System on Embedded Soft Processor for Space Applications. ARCS (2022)
Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process. DFT (2022)
Luca Sterpone, Sarah Azimi, Corrado De Sio, Filippo Parisi
Analysis and Mitigation of Soft-Errors on High Performance Embedded GPUs. ISPDC (2022)
Sarah Azimi, Corrado De Sio, Luca Sterpone
A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC. SMACD (2022)
Andrea Portaluri, Sarah Azimi, Corrado De Sio, Luca Sterpone, David Merodio Codinachs
Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices. IOLTS (2022)
Corrado De Sio, Sarah Azimi, Luca Sterpone
FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Marcio M. Gonçalves, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone, José Rodrigo Azambuja
Evaluating low-level software-based hardening techniques for configurable GPU architectures. J. Supercomput. 78 (6) (2022)
Boyang Du, Sarah Azimi, Annarita Moramarco, Davide Sabena, Filippo Parisi, Luca Sterpone
An Automated Continuous Integration Multitest Platform for Automotive Systems. IEEE Syst. J. 16 (2) (2022)
Ludovica Bozzoli, Corrado De Sio, Boyang Du, Luca Sterpone
A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs. I2MTC (2021)
Sarah Azimi, Corrado De Sio, Luca Sterpone
On the Evaluation of SEEs on Open-Source Embedded Static RAMs. VLSI-SoC (2021)
Sarah Azimi, Corrado De Sio, Andrea Portaluri, Luca Sterpone
Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs. VLSI-SoC (Selected Papers) (2021)
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability. J. Supercomput. 77 (10) (2021)
Sarah Azimi, Corrado De Sio, Luca Sterpone
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor. DATE (2021)
Sarah Azimi, Corrado De Sio, Luca Sterpone
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. IEEE Trans. Very Large Scale Integr. Syst. 29 (8) (2021)
Andrea Portaluri, Corrado De Sio, Sarah Azimi, Luca Sterpone
A New Domains-based Isolation Design Flow for Reconfigurable SoCs. IOLTS (2021)
Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor. DFT (2021)
Sarah Azimi, Luca Sterpone
Digital Design Techniques for Dependable High Performance Computing. ITC (2020)
Josie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets. ISVLSI (2020)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. CoRR (2020)
Corrado De Sio, Sarah Azimi, Luca Sterpone
An Emulation Platform for Evaluating the Reliability of Deep Neural Networks. DFT (2020)
Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. CoRR (2020)
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs. VTS (2020)
Corrado De Sio, Sarah Azimi, Luca Sterpone
On the Evaluation of SEU Effects on AXI Interconnect Within AP-SoCs. ARCS (2020)
Sarah Azimi, Corrado De Sio, Luca Sterpone
In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops. IOLTS (2020)
Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE (2020)
Ludovica Bozzoli, Luca Sterpone
An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs. IEEE Access 8 (2020)
Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs. DDECS (2020)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. CoRR (2020)
Sarah Azimi, Corrado De Sio, Weitao Yang, Luca Sterpone
A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit. NEWCAS (2020)
Ludovica Bozzoli, Luca Sterpone
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs. ARC (2020)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. CoRR (2020)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. IOLTS (2020)
Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU. LATS (2020)
Corrado De Sio, Sarah Azimi, Luca Sterpone, Boyang Du
Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect. IEEE Access 7 (2019)
Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. DTIS (2019)
Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs. Integr. 67 (2019)
Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network. DDECS (2019)
Corrado De Sio, Sarah Azimi, Luca Sterpone
On the Evaluation of the PIPB Effect within SRAM-based FPGAs. ETS (2019)
Ludovica Bozzoli, Luca Sterpone
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures. ARC (2019)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. IOLTS (2019)
Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. DSN (Supplements) (2019)
Luca Sterpone, Ludovica Bozzoli, Corrado De Sio, Boyang Du, Sarah Azimi
A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs. SMACD (2019)
Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
On the evaluation of SEU effects in GPGPUs. LATS (2019)
Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR (2019)
Boyang Du, Sarah Azimi, Corrado De Sio, Ludovica Bozzoli, Luca Sterpone
On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA. DFT (2019)
Luca Sterpone, Ludovica Bozzoli
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach. ARC (2018)
Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. AHS (2018)
Sarah Azimi, Luca Sterpone, Boyang Du, Luca Boragno
On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs. Microelectron. Reliab. (2018)
Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Cinzia Bernardeschi
PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing. RSP (2018)
Sarah Azimi, Boyang Du, Luca Sterpone
On the mitigation of single event transients on flash-based FPGAs. ETS (2018)
Ludovica Bozzoli, Luca Sterpone
MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories. DFT (2018)
Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, L. Cattaneo
SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs. SMACD (2018)
Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
About the functional test of the GPGPU scheduler. IOLTS (2018)
Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Andrea Domenici, Cinzia Bernardeschi, Luca Sterpone, Mario Porrmann
: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. IEEE Trans. Emerg. Top. Comput. 6 (4) (2018)
Ludovica Bozzoli, Luca Sterpone
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs. ISCAS (2018)
Ludovica Bozzoli, Luca Sterpone
Self rerouting of dynamically reconfigurable SRAM-based FPGAs. AHS (2017)
Qiutao Zhang, Sarah Azimi, Germano La Vaccara, Luca Sterpone, Boyang Du
A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA. Microelectron. Reliab. (2017)
Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs. ACM Great Lakes Symposium on VLSI (2017)
Sarah Azimi, Luca Sterpone
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach. ISVLSI (2017)
Sarah Azimi, Annarita Moramarco, Luca Sterpone
Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs. ISIE (2017)
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers 66 (6) (2017)
Sarah Azimi, Boyang Du, Luca Sterpone
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment. J. Syst. Archit. 75 (2017)
Boyang Du, Luca Sterpone
Online monitoring soft errors in reconfigurable FPGA during radiation test. I2MTC (2017)
Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. J. Syst. Archit. 81 (2017)
Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andres Cardona, Carles Ferrer
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectron. Reliab. 75 (2017)
Luca Sterpone, Luca Boragno
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs. IOLTS (2017)
Boyang Du, Luca Sterpone
Fault tolerant electronic system design. ITC (2017)
Luca Sterpone, Luca Boragno
A probe-based SEU detection method for SRAM-based FPGAs. Microelectron. Reliab. (2017)
Luca Sterpone, Gianpiero Cabodi, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Boyang Du
Scalable FPGA graph model to detect routing faults. IOLTS (2016)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. Integr. 55 (2016)
Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda
Hybrid soft error mitigation techniques for COTS processor-based systems. LATS (2016)
Sarah Azimi, Boyang Du, Luca Sterpone
A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs. ARCS (2016)
Boyang Du, Luca Sterpone, David Merodio Codinachs
A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs. ETS (2016)
Luca Sterpone, Luca Boragno, David Merodio Codinachs
Analysis of radiation-induced SEUs on dynamic reconfigurable systems. ReCoSoC (2016)
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65 (6) (2016)
Sarah Azimi, Boyang Du, Luca Sterpone
On the prediction of radiation-induced SETs in flash-based FPGAs. Microelectron. Reliab. 64 (2016)
Boyang Du, Luca Sterpone
An FPGA-based testing platform for the validation of automotive powertrain ECU. VLSI-SoC (2016)
Luca Sterpone, Boyang Du
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs. ARC (2015)
Boyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs
On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs. ReCoSoC (2015)
Luca Sterpone, Boyang Du, Sarah Azimi
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies. Microelectron. Reliab. 55 (9-10) (2015)
Dan Alexandrescu, Luca Sterpone, Celia López-Ongil
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. ETS (2014)

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Publication Activity (10 Years)

Top Topics

Top Venues

Luca Sterpone