Luca Cassano

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 40

Top Topics

Image Processing

Fault Detection

Computing Paradigms

Top Venues

IEEE Trans. Computers

Publications

Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. DATE (2024)
Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. ETS (2024)
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
Optimizing the Use of Behavioral Locking for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Cristiana Bolchini, Luca Cassano, Antonio Miele
Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques. CoRR (2023)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi
Fast and Accurate Error Simulation for CNNs Against Soft Errors. IEEE Trans. Computers 72 (4) (2023)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications. DFT (2023)
Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola
Towards Dependable RISC-V Cores for Edge Computing Devices. IOLTS (2023)
Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. DFT (2023)
Alessandro Palumbo, Marco Ottavi, Luca Cassano
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. DFT (2023)
Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. DDECS (2022)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi
Fast and Accurate Error Simulation for CNNs against Soft Errors. CoRR (2022)
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
Approximation-Based Fault Tolerance in Image Processing Applications. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE Trans. Very Large Scale Integr. Syst. 30 (7) (2022)
Alessandro Palumbo, Luca Cassano, Bruno Luzzi, José Alberto Hernández, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. J. Syst. Archit. 128 (2022)
Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena Ioana Vatajelu
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? DDECS (2022)
Cristiana Bolchini, Giacomo Boracchi, Luca Cassano, Antonio Miele, Diego Stucchi
Fault Impact Estimation for Lightweight Fault Detection in Image Filtering. IEEE Trans. Computers 71 (2) (2022)
Luca Cassano, Antonio Miele, Francesco Mione, Nicola Tonellotto, Carlo Vallati
Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments. IEEE Embed. Syst. Lett. 14 (2) (2022)
Antonio Miele, Henry Zárate, Luca Cassano, Cristiana Bolchini, Jorge Eduardo Ortiz Trivino
A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures. ACM Trans. Internet Things 3 (3) (2022)
Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
Is RISC-V ready for Space? A Security Perspective. DFT (2022)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari
Selective Hardening of CNNs based on Layer Vulnerability Estimation. DFT (2022)
Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale
DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN. J. Syst. Archit. 129 (2022)
Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. DFT (2021)
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
On the Optimization of Behavioral Logic Locking for High-Level Synthesis. CoRR (2021)
Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications. DFT (2021)
Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. IOLTS (2020)
Giacomo Tanganelli, Luca Cassano, Antonio Miele, Carlo Vallati
A methodology for the design and deployment of distributed cyber-physical systems for smart environments. Future Gener. Comput. Syst. 109 (2020)
Matteo Biasielli, Luca Cassano, Antonio Miele
An Approximation-based Fault Detection Scheme for Image Processing Applications. DATE (2020)
Ana Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano
Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis. IOLTS (2020)
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Erdem Koyuncu, Antonio Miele
A Neural Network Based Fault Management Scheme for Reliable Image Processing. IEEE Trans. Computers 69 (5) (2020)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Matteo Biasielli
Lightweight Fault Detection and Management for Image Restoration. DFT (2020)
Alperen Bolat, Luca Cassano, Pedro Reviriego, Oguz Ergin, Marco Ottavi
A Microprocessor Protection Architecture against Hardware Trojans in Memories. DTIS (2020)
Ana Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano
Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking. DFT (2019)
Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale
HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems. IOLTS (2019)
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Antonio Miele
A Smart Fault Detection Scheme for Reliable Image Processing Applications. DATE (2019)
Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Andrea Domenici, Cinzia Bernardeschi, Luca Sterpone, Mario Porrmann
: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. IEEE Trans. Emerg. Top. Comput. 6 (4) (2018)
Cristiana Bolchini, Luca Cassano
A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis. IEEE Des. Test 34 (2) (2017)
Cristiana Bolchini, Luca Cassano, Antonio Miele
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. DATE (2016)
Cristiana Bolchini, Luca Cassano
A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards. IEEE Trans. Computers 65 (1) (2016)
Marco Avvenuti, Cinzia Bernardeschi, Luca Cassano, Alessio Vecchio
Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation. Ad Hoc Sens. Wirel. Networks 31 (1-4) (2016)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. Integr. 55 (2016)
Cristiana Bolchini, Luca Cassano, Paolo Garza, Elisa Quintarelli, Fabio Salice
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies. J. Comput. Sci. Technol. 30 (2) (2015)
Cristiana Bolchini, Luca Cassano
A configurable board-level adaptive incremental diagnosis technique based on decision trees. DFTS (2015)
Luca Cassano, Hipólito Guzmán-Miranda, Miguel A. Aguirre
Early assessment of SEU sensitivity through untestable fault identification. IOLTS (2014)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (9) (2014)
Luca Cassano
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. ITC (2014)
Luca Cassano, Alberto Bosio, Giorgio Di Natale
A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS (2014)
Domenico G. Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi
Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. DFT (2014)
Luca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi
An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems. DTIS (2014)
Cristiana Bolchini, Luca Cassano
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis. DFT (2014)
Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries. IEEE Trans. Ind. Informatics 10 (2) (2014)
Daniel Cesarini, Luca Cassano, Alessio Fagioli, Marco Avvenuti
Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations. ES4CPS@DATE (2014)
Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries. IECON (2013)
Cinzia Bernardeschi, Luca Cassano, Mario G. C. A. Cimino, Andrea Domenici
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs. J. Syst. Archit. 59 (10-D) (2013)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. ACM Great Lakes Symposium on VLSI (2013)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
Formal approaches to SEU testing in FPGAs. AHS (2013)
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone
On-line testing of permanent radiation effects in reconfigurable systems. DATE (2013)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. DFT (2012)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
SEU-X: A SEu un-excitability prover for SRAM-FPGAs. IOLTS (2012)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
Failure Probability and Fault Observability of SRAM-FPGA Systems. FPL (2011)
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. DDECS (2011)