Michele Favalli

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 7

Top Topics

Boolean Satisfiability

Confidence Scores

Integrated Circuit

Top Venues

IET Comput. Digit. Tech.

Publications

Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. ETS (2024)
Elena Bellodi, Davide Bertozzi, Alice Bizzarri, Michele Favalli, Michele Fraccaroli, Riccardo Zese
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach. MCSoC (2023)
Alessandro Veronesi, Francesco Dall'Occo, Davide Bertozzi, Michele Favalli, Milos Krstic
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study. DDECS (2022)
Francesco Dall'Occo, Andrés Bueno-Crespo, José L. Abellán, Davide Bertozzi, Michele Favalli
The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks. SAMOS (2021)
Marcello Dalpasso, Davide Bertozzi, Michele Favalli
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices. DATE (2018)
Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi
A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations. NOCS (2016)
Michele Favalli, Marcello Dalpasso
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults. IEEE Trans. Computers 65 (3) (2016)
L. Valenti, Marcello Dalpasso, Michele Favalli
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits. IET Comput. Digit. Tech. 8 (2) (2014)
Michele Favalli, Marcello Dalpasso
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits. J. Electron. Test. 30 (1) (2014)
Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12 (4) (2013)
Alberto Ghiribaldi, Alessandro Strano, Michele Favalli, Davide Bertozzi
Power efficiency of switch architecture extensions for fault tolerant NoC design. IGCC (2012)
Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. VLSI-SoC (2011)
Santino Mele, Michele Favalli
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. DATE (2011)
Michele Favalli, Marcello Dalpasso
How Many Test Vectors We Need to Detect a Bridging Fault? J. Electron. Test. 25 (1) (2009)
Michele Favalli, Cecilia Metra
Testing Resistive Opens and Bridging Faults Through Pulse Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (6) (2009)
Michele Favalli, Marcello Dalpasso
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. DFT (2007)
Michele Favalli
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. DFT (2007)
Michele Favalli, Cecilia Metra
Interactive presentation: Pulse propagation for the detection of small delay defects. DATE (2007)
Michele Favalli
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems. IEEE Trans. Computers 55 (3) (2006)
Michele Favalli
A fuzzy model for path delay fault detection. IEEE Trans. Very Large Scale Integr. Syst. 13 (8) (2005)
Michele Favalli
Annotated Bit Flip Fault Model. DFT (2004)
Michele Favalli
"Victim Gate" Crosstalk Fault Model. DFT (2004)
Michele Favalli, Cecilia Metra
TMR voting in the presence of crosstalk faults at the voter inputs. IEEE Trans. Reliab. 53 (3) (2004)
Cecilia Metra, Luca Schiano, Michele Favalli
Concurrent detection of power supply noise. IEEE Trans. Reliab. 52 (4) (2003)
Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. Microelectron. J. 34 (1) (2003)
Michele Favalli, Cecilia Metra
Online Testing Approach for Very Deep-Submicron ICs. IEEE Des. Test Comput. 19 (2) (2002)
Michele Favalli, Marcello Dalpasso
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators. DATE (2002)
Michele Favalli, Cecilia Metra
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. J. Electron. Test. 18 (3) (2002)
Michele Favalli, Cecilia Metra
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. DATE (2002)
Michele Favalli, Marcello Dalpasso
Bridging fault modeling and simulation for deep submicron CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (8) (2002)
Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò
On-Chip Clock Faults' Detector. J. Electron. Test. 18 (4-5) (2002)
Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli
Self-Checking Scheme for the On-Line Testing of Power Supply Noise. DATE (2002)
Michele Favalli, Cecilia Metra
Optimization of error detecting codes for the detection of crosstalk originated errors. DATE (2001)
Michele Favalli, Cecilia Metra
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. IOLTW (2001)
Cecilia Metra, Michele Favalli, Bruno Riccò
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. VLSI Design 2000 (1) (2000)
Cecilia Metra, Michele Favalli, Bruno Riccò
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. DATE (2000)
Michele Favalli, Cecilia Metra
Bridging Faults in Pipelined Circuits. J. Electron. Test. 16 (6) (2000)
Cecilia Metra, Michele Favalli, Bruno Riccò
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. IEEE Trans. Computers 49 (6) (2000)
Alessandro Bogliolo, Michele Favalli, Maurizio Damiani
-checkable voters. IEEE Trans. Very Large Scale Integr. Syst. 8 (4) (2000)
Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli
Virtual Fault Simulation of Distributed IP-Based Designs. DATE (2000)
Michele Favalli, Cecilia Metra
On the Design of Self-Checking Functional Units Based on Shannon Circuits. DATE (1999)
Michele Favalli, Cecilia Metra
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Cecilia Metra, Michele Favalli, Bruno Riccò
Concurrent Checking of Clock Signal Correctness. IEEE Des. Test Comput. 15 (4) (1998)
Cecilia Metra, Michele Favalli, Bruno Riccò
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. DFT (1998)
Cecilia Metra, Michele Favalli, Bruno Riccò
On-line detection of logic errors due to crosstalk, delay, and transient faults. ITC (1998)
Cecilia Metra, Michele Favalli, Bruno Riccò
Highly Testable and Compact 1-out-of-n Code Checker with Single Output. DATE (1998)
Luca Benini, Alessandro Bogliolo, Michele Favalli, Giovanni De Micheli
Regression Models for Behavioral Power Estimation. Integr. Comput. Aided Eng. 5 (2) (1998)
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Cecilia Metra, Michele Favalli, Bruno Riccò
Highly testable and compact single output comparator. VTS (1997)
Marcello Dalpasso, Michele Favalli
testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (10) (1997)
Cecilia Metra, Michele Favalli, Bruno Riccò
Compact and low power on-line self-testing voting scheme. DFT (1997)
Michele Favalli, Cecilia Metra
Testing scheme for IC's clocks. ED&TC (1997)
Michele Favalli, Marcello Dalpasso
Symbolic Handling of Bridging Fault Effects. J. Electron. Test. 10 (3) (1997)
Michele Favalli, Cecilia Metra
Low-level error recovery mechanism for self-checking sequential circuits. DFT (1997)
Cecilia Metra, Michele Favalli, Bruno Riccò
On-Line Testing Scheme for Clock's Faults. ITC (1997)
Michele Favalli, Marcello Dalpasso, Piero Olivo
Modeling and simulation of broken connections in CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (7) (1996)
Michele Favalli, Luca Benini, Giovanni De Micheli
Design for Testability of Gated-Clock FSMs. ED&TC (1996)
Michele Favalli, Cecilia Metra
Sensing circuit for on-line detection of delay faults. IEEE Trans. Very Large Scale Integr. Syst. 4 (1) (1996)
Cecilia Metra, Michele Favalli, Bruno Riccò
Tree Checkers for Applications with Low Power-Delay Requirements. DFT (1996)
Cecilia Metra, Michele Favalli, Bruno Riccò
Embedded two-rail checkers with on-line testing ability. VTS (1996)
Cecilia Metra, Michele Favalli, Bruno Riccò
Compact and Highly Testable Error Indicator for Self-Checking Circuits. DFT (1996)
Michele Favalli, Bruno Riccò, L. Penza
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs. ED&TC (1995)
Marcello Dalpasso, Michele Favalli, Piero Olivo
: increasing test quality. VTS (1995)
Cecilia Metra, Michele Favalli, Bruno Riccò
Novel Berger code checker. DFT (1995)
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J. Electron. Test. 6 (1) (1995)
Marcello Dalpasso, Michele Favalli, Piero Olivo
testing quality and sensor accuracy. ED&TC (1995)
Michele Favalli, Luca Benini
Analysis of glitch power dissipation in CMOS ICs. ISLPD (1995)
Cecilia Metra, Michele Favalli, Bruno Riccò
Highly Testable and Compact 1-out-of-n CMOS Checkers. DFT (1994)
Cecilia Metra, Michele Favalli, Bruno Riccò
CMOS Self Checking Circuits with Faulty Sequential Functional Block. DFT (1994)
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
Modeling of Broken Connections Faults in CMOS ICs. EDAC-ETC-EUROASIC (1994)
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
Analysis of resistive bridging fault detection in BiCMOS digital ICs. IEEE Trans. Very Large Scale Integr. Syst. 1 (3) (1993)
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs. ITC (1993)
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
A Highly Testable 1-out-of-3 CMOS Checker. DFT (1993)
Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
Fault simulation of parametric bridging faults in CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. DFT (1993)
Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
Testability measures in pseudorandom testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (6) (1992)
Michele Favalli, Piero Olivo, Bruno Riccò
A probabilistic fault model for 'analog' faults in digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (11) (1992)
Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. ITC (1992)
Michele Favalli, Piero Olivo, Bruno Riccò
Dynamic effects in the detection of bridging faults in CMOS ICs. J. Electron. Test. 3 (3) (1992)
Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs. ITC (1992)
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs. ITC (1992)
Michele Favalli, Piero Olivo, Bruno Riccò
A novel critical path heuristic for fast fault grading. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (4) (1991)
Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
Fault simulation of unconventional faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (5) (1991)
Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi
Fault simulation for general FCMOS ICs. J. Electron. Test. 2 (2) (1991)
M. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò
Detection of PLA multiple crosspoint faults. EURO-DAC (1991)
Michele Favalli, Piero Olivo, Bruno Riccò
A probabilistic fault model for analog faults. EURO-DAC (1991)
Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò
Aliasing in signature analysis testing with multiple input shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (12) (1990)
Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
An analytical model for the aliasing probability in signature analysis testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (11) (1989)
Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
CMOS Design for Improved IC Testability. ITC (1989)
Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
Improved testability evaluations in combinational logic networks. ICCD (1989)
Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
Aliasing errors in signature analysis testing of integrated circuits. ICCD (1988)