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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Alessandro Strano
Crispín Gómez Requena
Daniele Ludovici
Michele Favalli
María Engracia Gómez
Davide Bertozzi
Published in:
DATE (2011)
Keyphrases
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network on chip
cooperative
multi processor
routing algorithm
packet switched
network simulator
single processor
real time
data transfer
shared memory
built in self test
image processing
data management
power dissipation
multi core processors
interconnection networks