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Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.
Cecilia Metra
Michele Favalli
Piero Olivo
Bruno Riccò
Published in:
J. Electron. Test. (1995)
Keyphrases
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circuit design
high speed
low power
design process
neural network
building blocks
design decisions
knowledge based systems
computer aided
design considerations
power dissipation
data sets
fuzzy logic
software architecture
single chip