José Flich

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 22

Top Topics

Dependency Graph

Computing Platform

Top Venues

Microprocess. Microsystems

Publications

Jie Lei, José Flich, Enrique S. Quintana-Ortí
Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal. PDP (2023)
David Rodriguez, Rafael Tornero, José Flich
Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms. DATE (2023)
Jie Lei, José Flich, Enrique S. Quintana-Ortí
Toward matrix multiplication for deep learning inference on the Xilinx Versal. CoRR (2023)
Rafael Tornero, David Rodriguez, José Maria Martínez, José Flich
An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration. DCIS (2023)
Jie Lei, Héctor Martínez, José Flich, Enrique S. Quintana-Ortí
GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal. ISC Workshops (2023)
Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE (2023)
Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe
Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence. Future Gener. Comput. Syst. 134 (2022)
Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe
Enabling Dynamic and Intelligent Workflows for HPC, Data Analytics, and AI Convergence. CoRR (2022)
José Flich, Laura Medina, Izan Catalán, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau, David Briand
Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. ICIP (2022)
Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortés, José Flich, José Duato
UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. J. Supercomput. 77 (11) (2021)
Tomás Picornell, José Flich, Carles Hernández, José Duato
Enforcing Predictability of Many-Cores With DCFNoC. IEEE Trans. Computers 70 (2) (2021)
José Flich, Rafael Tornero, D. Rodriguez, D. Russo, José Maria Martínez, Carles Hernández
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. DATE (2021)
Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich, José Duato
UPR: Deadlock-Free Dynamic Network Reconfiguration by Exploiting Channel Dependency Graph Compatibility. CoRR (2020)
Carles Hernández, José Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Lüdemann, Mikel Labayen
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. DSD (2020)
Juan-José Crespo, German Maglione Mathey, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich
TDSR: Transparent Distributed Segment-Based Routing. CoRR (2020)
José Flich, Carles Hernández, Eduardo Quiñones, Roberto Paredes
Distributed Training on a Highly Heterogeneous HPC System. SAMOS (2020)
Tomás Picornell, José Flich, Carles Hernández, José Duato
DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. DAC (2019)
Miguel Gorgues Alonso, José Flich, Meriem Turki, Davide Bertozzi
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems. MCSoC (2019)
Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. ACM J. Emerg. Technol. Comput. Syst. 15 (1) (2019)
José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61 (2018)
William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS (2018)
José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO (2017)
Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich
-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs. DATE (2015)
Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]. ACM Trans. Embed. Comput. Syst. 14 (1) (2015)
Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Des. Autom. Embed. Syst. 19 (1-2) (2015)
Marco Balboni, José Flich, Davide Bertozzi
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. DATE (2015)
Antoni Roca, Carles Hernández, Mario Lodde, José Flich
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. 45 (2015)
José V. Escamilla, José Flich, Pedro Javier García
Efficient DVFS Operation in NoCs Through a Proper Congestion Management Strategy. Euro-Par Workshops (2015)
Mario Lodde, José Flich
Runtime home mapping for effective memory resource usage. Microprocess. Microsystems 38 (4) (2014)
Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12 (4) (2013)
Francisco Triviño, Davide Bertozzi, José Flich
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs. INA-OCMC@HiPEAC (2013)
Mario Lodde, José Flich
A Lightweight Network of IDs to Quickly Deliver Simple Control Messages. Euro-Par Workshops (2013)
Mario Lodde, Antoni Roca, José Flich
Built-in fast gather control network for efficient support of coherence protocols. IET Comput. Digit. Tech. 7 (2) (2013)
Bartosz Bogdanski, Bjørn Dag Johnsen, Sven-Arne Reinemo, José Flich
Making the Network Scalable: Inter-subnet Routing in InfiniBand. Euro-Par (2013)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. 59 (7) (2013)
María Soler, José Flich
Power Saving by NoC Traffic Compression. Euro-Par Workshops (2013)
Mario Lodde, José Flich, Manuel E. Acacio
Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par (2013)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP (2012)
Qiaoyan Yu, José Cano, José Flich, Paul Ampadu
Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip. NOCS (2012)
Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich
Network-on-Chip virtualization in Chip-Multiprocessor Systems. J. Syst. Archit. 58 (3-4) (2012)
José Flich, Scott Pakin, Craig B. Stunkel
CASS Introduction. IPDPS Workshops (2012)
Albert Esteve, María Soler, María Engracia Gómez, Antonio Robles, José Flich
Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems. Euro-Par Workshops (2012)
Antoni Roca, José Flich, Giorgos Dimitrakopoulos
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL (2012)
José Flich, Scott Pakin, Craig B. Stunkel
Special issue on Communication Architectures for Scalable Systems. J. Parallel Distributed Comput. 72 (11) (2012)
Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich
Exploring NoC Virtualization Alternatives in CMPs. PDP (2012)
Alessandro Strano, Davide Bertozzi, Federico Angiolini, Leonardo Di G. Gregorio, Frank Olaf Sem-Jacobsen, Vladimir Todorov, José Flich, José Silla, Tobias Bjerregaard
Quest for the ultimate network-on-chip: the NaNoC project. INA-OCMC@HiPEAC (2012)
Mario Lodde, Toni Roca, José Flich
Heterogeneous network design for effective support of invalidation-based coherency protocols. INA-OCMC@HiPEAC (2012)
Antoni Roca, José Flich, Federico Silla, José Duato
A low-latency modular switch for CMP systems. Microprocess. Microsystems 35 (8) (2011)
J. Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski
A power-efficient network on-chip topology. INA-OCMC@HiPEAC (2011)
Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski
Towards an Efficient NoC Topology through Multiple Injection Ports. DSD (2011)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
A Distributed Switch Architecture for On-Chip Networks. ICPP (2011)
Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurr. Comput. Pract. Exp. 23 (17) (2011)
Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot
Spidergon STNoC design flow. NOCS (2011)
Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich
Virtualizing network-on-chip resources in chip-multiprocessors. Microprocess. Microsystems 35 (2) (2011)
José Flich, Scott Pakin, Craig B. Stunkel
CASS Introduction. IPDPS Workshops (2011)
Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. 71 (5) (2011)
Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich
A fast centralized computation routing algorithm for self-configuring NoC systems. HiPC (2011)
Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees. J. Parallel Distributed Comput. 71 (11) (2011)
José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli
Efficient routing implementation in complex systems-on-chip. NOCS (2011)
Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich
NoC Reconfiguration for CMP Virtualization. NCA (2011)
Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato
PC-Mesh: A Dynamic Parallel Concentrated Mesh. ICPP (2011)
Antoni Roca, José Flich, Federico Silla, José Duato
VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. HiPC (2010)
Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. ICPADS (2010)
José Flich, Alfonso Urso, Ulrich Brüning, Giuseppe Di Fatta
High Performance Networks. Euro-Par (2) (2010)
Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato
Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digit. Tech. 3 (5) (2009)
Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, Wladek Olesinski
A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors. NoCArc@MICRO (2009)
Tor Skeie, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, José Flich, Davide Bertozzi, Simone Medardoni
Flexible DOR routing for virtualization of multicore chips. SoC (2009)
José Flich, José Duato
Logic-Based Distributed Routing for NoCs. IEEE Comput. Archit. Lett. 7 (1) (2008)
José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne
On the Potential of NoC Virtualization for Multicore Chips. Scalable Comput. Pract. Exp. 9 (3) (2008)
José Miguel Montañana, José Flich, Antonio Robles, José Duato
A Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks. ISHPC (2005)