Antoni Roca

Publication Activity (10 Years)

Years Active: 2010-2017
Publications (10 Years): 5

Top Topics

Hierarchical Architecture

Gigabit Ethernet

Multi Agent Architecture

Top Venues

IET Comput. Digit. Tech.

Comput. Electr. Eng.

J. Syst. Archit.

Publications

Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella
DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. DAC (2017)
Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
Ring Oscillator Clocks and Margins. ASYNC (2016)
Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla
Improving performance guarantees in wormhole mesh NoC designs. DATE (2016)
Antoni Roca, Carles Hernández, Mario Lodde, José Flich
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. 45 (2015)
Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
Reactive clocks with variability-tracking jitter. ICCD (2015)
Javier de San Pedro, Jordi Cortadella, Antoni Roca
A hierarchical approach for generating regular floorplans. ICCAD (2014)
José Cano, Jose Flich, Antoni Roca, José Duato, Marcello Coppola, Riccardo Locatelli
Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. IEEE Trans. Computers 63 (3) (2014)
Mario Lodde, Antoni Roca, José Flich
Built-in fast gather control network for efficient support of coherence protocols. IET Comput. Digit. Tech. 7 (2) (2013)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. 59 (7) (2013)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP (2012)
Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Antoni Roca, José Flich, Giorgos Dimitrakopoulos
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL (2012)
Antoni Roca, José Flich, Federico Silla, José Duato
A low-latency modular switch for CMP systems. Microprocess. Microsystems 35 (8) (2011)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
A Distributed Switch Architecture for On-Chip Networks. ICPP (2011)
Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. 71 (5) (2011)
Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, José Duato
Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Comput. Archit. Lett. 10 (2) (2011)
Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato
PC-Mesh: A Dynamic Parallel Concentrated Mesh. ICPP (2011)
Antoni Roca, José Flich, Federico Silla, José Duato
VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. HiPC (2010)
Antoni Roca, Jose Flich, Federico Silla, José Duato
A Latency-Efficient Router Architecture for CMP Systems. DSD (2010)
Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS (2010)
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. NOCS (2010)