Carles Hernández

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 76

Top Topics

Random Number Generators

Replacement Policy

Computing Platform

Top Venues

Publications

Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE (2023)
Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández
BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. DATE (2023)
Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó
A Security Model for Randomization-based Protected Caches. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (3) (2022)
Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó
A Security Model for Randomization-based Protected Caches. IACR Cryptol. ePrint Arch. 2022 (2022)
Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
Achieving Diverse Redundancy for GPU Kernels. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francesc Serra-Graells, Nehir Sönmez, Lluís Terés, Osman Unsal, Mateo Valero, Luís Villa
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS (2022)
Guillem Cabo, Sergi Alcaide, Carles Hernández, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella
SafeSU-2: a Safe Statistics Unit for Space MPSoCs. DATE (2022)
José Flich, Laura Medina, Izan Catalán, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau, David Briand
Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. ICIP (2022)
Laura Medina, Salva Carrion, Pablo Andreu, Tomás Picornell, Jose Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess, Herbert Taucher
The SELENE Deep Learning Acceleration Framework for Safety-related Applications. DATE (2022)
Pablo Andreu, Carles Hernández, Tomás Picornell, Pedro López, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella
End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. CoRR (2022)
Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández
HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. FPL (2021)
Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moretó, Carles Hernández, Jaume Abella
SafeSU: an Extended Statistics Unit for Multicore Timing Interference. ETS (2021)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. IEEE Trans. Sustain. Comput. 6 (3) (2021)
Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, Jose Flich, Carles Hernández
Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD (2021)
Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Mike Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS (2021)
Tomás Picornell, José Flich, Carles Hernández, José Duato
Enforcing Predictability of Many-Cores With DCFNoC. IEEE Trans. Computers 70 (2) (2021)
José Flich, Rafael Tornero, D. Rodriguez, D. Russo, José Maria Martínez, Carles Hernández
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. DATE (2021)
Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS (2020)
Carles Hernández, Jaume Abella, Mikel Azkarate-askasua, Roman Obermaisser
Workshop on High-performance Computing Platforms for Dependable Autonomous Systems. DSN Workshops (2020)
Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms. DFT (2020)
Carles Hernández, José Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Lüdemann, Mikel Labayen
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. DSD (2020)
Tomás Picornell, Jose Flich, José Duato, Carles Hernández
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory. IEEE Access 8 (2020)
Sergi Alcaide Portet, Leonidas Kosmidis, Carles Hernández, Jaume Abella
Software-Only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms. DSN (Supplements) (2020)
José Flich, Carles Hernández, Eduardo Quiñones, Roberto Paredes
Distributed Training on a Highly Heterogeneous HPC System. SAMOS (2020)
Ramon Canal, Carles Hernández, Rafael Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech Piatek, Jaume Abella
Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives. ACM Comput. Surv. 53 (5) (2020)
Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
The RECIPE approach to challenges in deeply heterogeneous high performance systems. Microprocess. Microsystems 77 (2020)
Tomás Picornell, José Flich, Carles Hernández, José Duato
DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. DAC (2019)
Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement. DATE (2019)
Pedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla
Towards limiting the impact of timing anomalies in complex real-time processors. ASP-DAC (2019)
Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, Jose Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
Challenges in Deeply Heterogeneous High Performance Systems. DSD (2019)
Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Tullio Vardanega
Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Comput. Surv. 52 (1) (2019)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. DSD (2019)
David Trilla, Francisco J. Cazorla, Carles Hernández, Jaume Abella
Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors. IEEE Des. Test 36 (6) (2019)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. DSD (2019)
Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Locality-aware cache random replacement policies. J. Syst. Archit. 93 (2019)
Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
High-Integrity GPU Designs for Critical Real-Time Automotive Systems. DATE (2019)
Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. DATE (2019)
Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Time-Randomized Wormhole NoCs for Critical Applications. ACM J. Emerg. Technol. Comput. Syst. 15 (1) (2019)
Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
Software-only Diverse Redundancy on GPUs for Autonomous Driving Platforms. IOLTS (2019)
Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernández, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. 67 (3) (2018)
Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Design and integration of hierarchical-placement multi-level caches for real-time systems. DATE (2018)
Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernández, Tullio Vardanega, Guillem Bernat
Reconciling Time Predictability and Performance in Future Computing Systems. IEEE Des. Test 35 (2) (2018)
Sergi Alcaide, Leonidas Kosmidis, Hamid Tabani, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain. IEEE Micro 38 (6) (2018)
Jordi Cardona, Carles Hernández, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores. RTSS (2018)
Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. ECRTS (2018)
Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Cache side-channel attacks and time-predictability in high-performance critical real-time systems. DAC (2018)
William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS (2018)
Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
RPR: a random replacement policy with limited pathological replacements. SAC (2018)
Mikel Fernández, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati
Probabilistic timing analysis on time-randomized platforms for the space domain. DATE (2017)
Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. DSD (2017)
Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella
DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. DAC (2017)
Enrico Mezzetti, Jaume Abella, Carles Hernández, Francisco J. Cazorla
Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling. RTSS (2017)
Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Francisco J. Cazorla
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding. Ada-Europe (2017)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Modelling bus contention during system early design stages. SIES (2017)
Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, Franck Wartel
Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. ECRTS (2017)
Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Design and implementation of a fair credit-based bandwidth sharing scheme for buses. DATE (2017)
Milos Panic, Jaume Abella, Eduardo Quiñones, Carles Hernández, Theo Ungerer, Francisco J. Cazorla
Adapting TDMA arbitration for measurement-based probabilistic timing analysis. Microprocess. Microsystems 52 (2017)
Jaime Espinosa, Carles Hernández, Jaume Abella
Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection. IOLTS (2016)
Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla
Random modulo: a new processor cache design for real-time critical systems. DAC (2016)
David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Resilient random modulo cache memories for probabilistically-analyzable real-time systems. IOLTS (2016)
Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD (2016)
Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernández, Andrea Gianarro, Ian Broster, Francisco J. Cazorla
Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems 47 (2016)
Milos Panic, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla
Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. RTAS (2016)
Mladen Slijepcevic, Mikel Fernández, Carles Hernández, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems. DSD (2016)
Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla
Improving performance guarantees in wormhole mesh NoC designs. DATE (2016)
Carles Hernández, Jaume Abella
Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Milos Panic, Jaume Abella, Carles Hernández, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla
Enabling TDMA Arbitration in the Context of MBPTA. DSD (2015)
Irune Agirre, Mikel Azkarate-askasua, Carles Hernández, Jaume Abella, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD (2015)
Jaime Espinosa, Carles Hernández, Jaume Abella, David de Andrés, Juan-Carlos Ruiz-Garcia
Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. DAC (2015)
Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, Tullio Vardanega
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES (2015)
Carles Hernández, Jaume Abella
Low-cost checkpointing in automotive safety-relevant systems. DATE (2015)
Antoni Roca, Carles Hernández, Mario Lodde, José Flich
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. 45 (2015)
Jaime Espinosa, Carles Hernández, Jaume Abella
Characterizing fault propagation in safety-critical processor designs. IOLTS (2015)
Milos Panic, Eduardo Quiñones, Carles Hernández, Jaume Abella, Francisco J. Cazorla
CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. DSD (2015)
Milos Panic, Eduardo Quiñones, Pavel G. Zaykov, Carles Hernández, Jaume Abella, Francisco J. Cazorla
Parallel many-core avionics systems. EMSOFT (2014)
Carles Hernández, Jaume Abella
LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems. DAC (2014)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. 59 (7) (2013)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP (2012)
Carles Hernández, Federico Silla, José Duato
Addressing Link Degradation in NoC-Based ULSI Designs. Euro-Par Workshops (2012)
Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
A Distributed Switch Architecture for On-Chip Networks. ICPP (2011)
Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. Int. J. Embed. Real Time Commun. Syst. 2 (4) (2011)
Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. 71 (5) (2011)
Carles Hernández, Federico Silla, José Duato
Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. ICPP (2011)
Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, José Duato
Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Comput. Archit. Lett. 10 (2) (2011)
Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. SoC (2010)
Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS (2010)
Carles Hernández, Federico Silla, José Duato
A methodology for the characterization of process variation in NoC links. DATE (2010)
Carles Hernández, Federico Silla, Vicente Santonja, José Duato
A new mechanism to deal with process variability in NoC links. IPDPS (2009)
Samuel Rodrigo, Carles Hernández, Jose Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai
Yield-oriented evaluation methodology of network-on-chip routing implementations. SoC (2009)