Sascha Uhrig

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 12

Top Venues

ARCS

ECRTS

ACM Trans. Embed. Comput. Syst.

RTCSA

University of Augsburg (PHD)

Education History

University of Augsburg

PHD

Publications

Fabien Geyer, Johannes Freitag, Tobias Schulz, Sascha Uhrig
Efficient and Mathematically Robust Operations for Certified Neural Networks Inference. CoRR (2024)
Daniel Schneider, Jens Braband, Erwin Schoitsch, Sascha Uhrig, Stefan Katzenbeisser
Safety and Security Coengineering in Embedded Systems. Secur. Commun. Networks 2019 (2019)
Johannes Freitag, Sascha Uhrig
Closed Loop Controller for Multicore Real-Time Systems. ARCS (2018)
Johannes Freitag, Sascha Uhrig, Theo Ungerer
Virtual Timing Isolation for Mixed-Criticality Systems. ECRTS (2018)
Alessandra Melani, Renato Mancuso, Marco Caccamo, Giorgio C. Buttazzo, Johannes Freitag, Sascha Uhrig
A scheduling framework for handling integrated modular avionic systems on multicore platforms. RTCSA (2017)
Ankit Agrawal, Gerhard Fohler, Johannes Freitag, Jan Nowotsch, Sascha Uhrig, Michael Paulitsch
Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. ECRTS (2017)
Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Ankit Agrawal, Gerhard Fohler, Jan Nowotsch, Sascha Uhrig, Michael Paulitsch
Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. RTAS (2016)
Werner Weber, Alfred Hoess, Jan van Deventer, Frank Oppenheimer, Rolf Ernst, Adam Kostrzewa, Philippe Dore, Thierry Goubier, Haris Isakovic, Norbert Druml, Egon Wuchner, Daniel Schneider, Erwin Schoitsch, Eric Armengaud, Thomas Soderqvist, Massimo Traversone, Sascha Uhrig, Juan Carlos Pérez-Cortes, Sergio Sáez, Juha Kuusela, Mark van Helvoort, Xing Cai, Bjørn Nordmoen, Geir Yngve Paulsen, Hans Petter Dahle, Michael Geissel, Jürgen Salecker, Peter Tummeltshammer
The EMC2 Project on Embedded Microcontrollers: Technical Progress after Two Years. DSD (2016)
Sascha Uhrig, Lillian Tadros, Arthur Pyka
MESI-Based Cache Coherence for Hard Real-Time Multicore Systems. ARCS (2015)
Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin
The shift to multicores in real-time and safety-critical systems. CODES+ISSS (2015)
Arthur Pyka, Pavel G. Zaykov, Hugues Cassé, Haluk Ozaktas, Christine Rochange, Sascha Uhrig
. INDIN (2015)
Arthur Pyka, Mathias Rohde, Sascha Uhrig
A real-time capable coherent data cache for multicores. Concurr. Comput. Pract. Exp. 26 (6) (2014)
Arthur Pyka, Mathias Rohde, Sascha Uhrig
Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems. ICSAMOS (2014)
Arthur Pyka, Mathias Rohde, Sascha Uhrig
Performance Evaluation of the Time Analysable On-Demand Coherent Cache. TrustCom/ISPA/IUCC (2013)
Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla
A hard real-time capable multi-core SMT processor. ACM Trans. Embed. Comput. Syst. 12 (3) (2013)
Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. DSD (2013)
Sascha Uhrig
Implementing a ring-based real-time capable network using a multithreaded Java processor. JTRES (2012)
Sascha Uhrig, Ralf Jahr, Theo Ungerer
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor. IET Comput. Digit. Tech. 6 (5) (2012)
Julian Wolf, Bernhard Fechner, Sascha Uhrig, Theo Ungerer
Fine-grained timing and control flow error checking for hard real-time task execution. SIES (2012)
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Julian Wolf, Theo Ungerer, Sascha Uhrig, Zlatko Petrov
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. ISORC (2011)
Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware. ARCS (2011)
Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer
RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor. Comput. Syst. Sci. Eng. 26 (6) (2011)
Sascha Uhrig
Tracing Static Fields of Embedded Parallel Java Applications. COMPSAC Workshops (2011)
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
Using SMT to Hide Context Switch Times of Large Real-Time Tasksets. RTCSA (2010)
Sascha Uhrig
The MANy JAva Core processor (MANJAC). HPCS (2010)
Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer
RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor. ISORC (2010)
Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. DSD (2010)
Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. ARCS (2010)
Florian Kluge, Sascha Uhrig, Jörg Mische, Benjamin Satzger, Theo Ungerer
Dynamic Workload Prediction for Soft Real-Time Applications. CIT (2010)
Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig
The embedded Java benchmark suite JemBench. JTRES (2010)
Florian Kluge, Sascha Uhrig, Jörg Mische, Benjamin Satzger, Theo Ungerer
Optimisation of Energy Consumption of Soft Real-Time Applications by Workload Prediction. ISORC Workshops (2010)
Ralf Jahr, Basher Shehan, Sascha Uhrig, Theo Ungerer
Static Speculation as Post-link Optimization for the Grid Alu Processor. Euro-Par Workshops (2010)
Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro 30 (5) (2010)
Sascha Uhrig
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. SAMOS (2009)
Sascha Uhrig, Theo Ungerer
A Garbage Collection Technique for Embedded Multithreaded Multicore Processors. ARCS (2009)
Sascha Uhrig
Risks and chances of many-core processors. HPCS (2009)
Florian Kluge, Chenglong Yu, Jörg Mische, Sascha Uhrig, Theo Ungerer
Implementing AUTOSAR scheduling and resource management on an embedded SMT processor. SCOPES (2009)
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. HiPEAC (2009)
Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. MEDEA@PACT (2008)
Sascha Uhrig
A Flexible Java-on-Chip Solution (Eine flexible Java-on-Chip Lösung). it Inf. Technol. 50 (5) (2008)
Florian Kluge, Sascha Uhrig, Jörg Mische, Theo Ungerer
A Two-Layered Management Architecture for Building Adaptive Real-Time Systems. SEUS (2008)
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
Exploiting spare resources of in-order SMT processors executing hard real-time threads. ICCD (2008)
Florian Kluge, Jörg Mische, Sascha Uhrig, Theo Ungerer
An Operating System Architecture for Organic Computing in Embedded Real-Time Systems. ATC (2008)
Sascha Uhrig, Jörg Mische, Theo Ungerer
An IP Core for Embedded Java Systems. SAMOS (2007)
Sascha Uhrig, Jörg Wiese
jamuth: an IP processor core for embedded Java real-time systems. JTRES (2007)
Sascha Uhrig, S. Maier, Georgi Kuzmanov, Theo Ungerer
Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. IPDPS (2006)
Uwe Brinkschulte, Sascha Uhrig, Theo Ungerer
Der mehrfädige Komodo-Mikrocontroller (The Multithreaded Komodo Microcontroller). it Inf. Technol. 47 (3) (2005)
Sascha Uhrig, Theo Ungerer
Energy Management for Embedded Multithreaded Processors with Integrated EDF Scheduling. ARCS (2005)
Sascha Uhrig, Theo Ungerer
Fine-grained power management for multithreaded processor cores. SAC (2004)
Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer
CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) (2004)
Jochen Kreuzinger, Uwe Brinkschulte, Matthias Pfeffer, Sascha Uhrig, Theo Ungerer
Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocess. Microsystems 27 (1) (2003)
Sascha Uhrig, Theo Ungerer
Hardware-based Power Management for Real-Time Applications. ISPDC (2003)
Matthias Pfeffer, Sascha Uhrig, Theo Ungerer, Uwe Brinkschulte
A Real-Time Java System on a Multithreaded Java Microcontroller. Symposium on Object-Oriented Real-Time Distributed Computing (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Sascha Uhrig