Benoît Dupont de Dinechin

Publication Activity (10 Years)

Years Active: 1991-2023
Publications (10 Years): 29

Top Topics

Cyclic Scheduling

Fast Fourier Transform

Massively Parallel

Processor Array

Top Venues

Publications

Benoît Dupont de Dinechin, Julien Hascoët, Orégane Desrentes
In-Place Multicore SIMD Fast Fourier Transforms. HPEC (2023)
Orégane Desrentes, Benoît Dupont de Dinechin, Julien Le Maire
Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning. DSD (2023)
Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin
Exact Fused Dot Product Add Operators. ARITH (2023)
Benoît Dupont de Dinechin
Computing In-Place FFTs with SIMD Lane Slicing. HPEC (2022)
Orégane Desrentes, Diana Resmerita, Benoît Dupont de Dinechin
A Posit8 Decompression Operator for Deep Neural Network Inference. CoNGA (2022)
Diana Resmerita, Rodrigo Cabral Farias, Benoît Dupont de Dinechin, Lionel Fillatre
Distortion Approximation of a Compressed Softmax Layer. SSP (2021)
Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara, Benoît Dupont de Dinechin
Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities. IEEE Signal Process. Mag. 38 (1) (2021)
Benoît Dupont de Dinechin
Engineering a Manycore Processor for Edge Computing. MECO (2021)
Matheus Schuh, Claire Maiza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. RTSS (2020)
Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge
Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. Perform. Evaluation 143 (2020)
Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin
Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip. RTNS (2019)
Benoît Dupont de Dinechin
Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor. DAC (2019)
Georgia Giannopoulou, Peter Poplavko, Dario Socci, Pengcheng Huang, Nikolay Stoimenov, Paraskevas Bourgos, Lothar Thiele, Marius Bozga, Saddek Bensalem, Sylvain Girbal, Madeleine Faugère, Romain Soulat, Benoît Dupont de Dinechin
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. Des. Autom. Embed. Syst. 22 (1-2) (2018)
Benoît Dupont de Dinechin
Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus. NOCS (2018)
Julien Hascoet, Benoît Dupont de Dinechin, Karol Desnos, Jean-François Nezan
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore. HPEC (2018)
Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin
Parallel code generation of synchronous programs for a many-core architecture. DATE (2018)
Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. PARMA-DITAM@HiPEAC (2018)
Benoît Dupont de Dinechin, Amaury Graillat
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor. AISTECS@HiPEAC (2017)
Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoît Dupont de Dinechin
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. DSD (2017)
Benoît Dupont de Dinechin, Amaury Graillat
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor. NoCArc@MICRO (2017)
Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin
Hierarchical Dataflow Model for efficient programming of clustered manycore processors. ASAP (2017)
Julien Hascoët, Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Minh Quan Ho
Asynchronous one-sided communications and synchronizations for a clustered manycore processor. ESTIMedia (2017)
Minh Quan Ho, Christian Obrecht, Bernard Tourancheau, Benoît Dupont de Dinechin, Julien Hascoet
Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors. IPCCC (2017)
Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele, Benoît Dupont de Dinechin
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. Real Time Syst. 52 (4) (2016)
Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin
Optimal and fast throughput evaluation of CSDF. DAC (2016)
Julien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin
Implementation of a Fast Fourier transform algorithm onto a manycore processor. DASIP (2015)
Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin
The shift to multicores in real-time and safety-critical systems. CODES+ISSS (2015)
Minh Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert
MPI communication on MPPA Many-core NoC: design, modeling and performance issues. PARCO (2015)
Benoît Dupont de Dinechin
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. Hot Chips Symposium (2015)
Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager
Time-critical computing on a single-chip massively parallel processor. DATE (2014)
Benoît Dupont de Dinechin, Alix Munier Kordon
Converging to periodic schedules for cyclic scheduling problems with resources and deadlines. Comput. Oper. Res. 51 (2014)
Benoît Dupont de Dinechin, Yves Durand, Duco van Amstel, Alexandre Ghiti
Guaranteed Services of the NoC of a Manycore Processor. NoCArc@MICRO (2014)
Benoît Dupont de Dinechin
Using the SSA-Form in a Code Generator. CC (2014)
Benoît Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Benoit Ganne, Pierre Guironnet de Massas, François Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frédéric Riss, Thierry Strudel
A clustered manycore processor architecture for embedded and accelerated applications. HPEC (2013)
Alix Munier Kordon, Fadi Kacem, Benoît Dupont de Dinechin, Lucian Finta
Scheduling an interval ordered precedence graph with communication delays and a limited number of processors. RAIRO Oper. Res. 47 (1) (2013)
Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert, Thierry Strudel
-256 Integrated Manycore Processor. ICCS (2013)
Pascal Aubry, Pierre-Edouard Beaucamps, Frédéric Blanc, Bruno Bodin, Sergiu Carpov, Loïc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benoît Dupont de Dinechin, François Galea, Thierry Goubier, Michel Harrand, Samuel Jones, Jean-Denis Lesage, Stéphane Louise, Nicolas Morey Chaisemartin, Thanh-Hai Nguyen, Xavier Raynaud, Renaud Sirdey
Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor. ICCS (2013)
Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin
Periodic schedules for Cyclo-Static Dataflow. ESTIMedia (2013)
Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta
Efficient liveness computation using merge sets and DJ-graphs. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin
K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph. ICSAMOS (2012)
Sid Ahmed Ali Touati, Frederic Brault, Karine Deschinkel, Benoît Dupont de Dinechin
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. ACM Trans. Embed. Comput. Syst. 10 (4) (2011)
Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello
A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. APLAS (2011)
Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon
Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency. CGO (2009)
Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello
Fast liveness checking for ssa-form programs. CGO (2008)
Benoît Dupont de Dinechin
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. Euro-Par (2008)
Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard
SCAN: A Heuristic for Near-Optimal Software Pipelining. Euro-Par (2006)
Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat
Division by Constant for the ST100 DSP Microprocessor. IEEE Symposium on Computer Arithmetic (2005)
Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin
Code generator optimizations for the ST120 DSP-MCU core. CASES (2000)
Benoît Dupont de Dinechin
Extending Modulo Scheduling with Memory Reference Merging. CC (1999)
Benoît Dupont de Dinechin
A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. LCPC (1997)
Robert W. Numrich, Jon L. Steidel, Brian H. Johnson, Benoît Dupont de Dinechin, Gary Elsesser, Greg Fischer, Tom MacDonald
Extension to Fortran 90. LCPC (1997)
Benoît Dupont de Dinechin
A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. PaCT (1997)
Benoît Dupont de Dinechin
Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates. LCPC (1996)
Benoît Dupont de Dinechin
Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers. LCPC (1995)
Benoît Dupont de Dinechin
An Introduction to Simplex Scheduling. IFIP PACT (1994)
Benoît Dupont de Dinechin
StaCS: a Static Control Superscalar architecture. MICRO (1992)
Benoît Dupont de Dinechin
A ultra fast Euclidean division algorithm for prime memory systems. SC (1991)