Jean-François Nezan

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 36

Top Topics

Hardware Implementation

Stereo Matching Algorithm

Fast Fourier Transform

Top Venues

J. Signal Process. Syst.

Publications

Joseph W. Faye, Naouel Haggui, Florent Kermarrec, Kevin J. M. Martin, Shuvra S. Bhattacharyya, Jean-François Nezan, Maxime Pelcat
Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming Applications. DASIP (2024)
Sunrise Wang, Nicolas Gac, Hugo Miomandre, Jean-François Nezan, Karol Desnos, François Orieux
An Initial Framework for Prototyping Radio-Interferometric Imaging Pipelines. DASIP (2024)
Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow. ACM Trans. Reconfigurable Technol. Syst. 17 (1) (2024)
Flavie Durand de Gevigney, Julien Heulot, Eric Bazin, Jean-François Nezan, Mickaël Dardaillon, Slaheddine Aridhi
A Highly Configurable Platform for Advanced PPG Analysis. DASIP (2024)
Naouel Haggui, Wassim Hamidouche, Fatma Belghith, Nouri Masmoudi, Jean-François Nezan
OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism. J. Signal Process. Syst. 95 (7) (2023)
Ophélie Renaud, Naouel Haggui, Karol Desnos, Jean-François Nezan
Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity. EUSIPCO (2023)
Ophélie Renaud, Dylan Gageot, Karol Desnos, Jean-François Nezan
SCAPE: HW-Aware Clustering of Dataflow Actors for Tunable Scheduling Complexity. DASIP (2023)
Hugo Miomandre, Jean-François Nezan, Daniel Ménard
Design Space Exploration for Memory-Oriented Approximate Computing Techniques. ASAP (2022)
Alexandre Honorat, Thomas Bourgoin, Hugo Miomandre, Karol Desnos, Daniel Ménard, Jean-François Nezan
Influence of Dataflow Graph Moldable Parameters on Optimization Criteria. DASIP (2022)
Naouel Haggui, Fatma Belghith, Wassim Hamidouche, Nouri Masmoudi, Jean-François Nezan
Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs. J. Signal Process. Syst. 94 (7) (2022)
Naouel Haggui, Fatma Belghith, Wassim Hamidouche, Nouri Masmoudi, Jean-François Nezan
Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs. DASIP (2021)
Alexandre Honorat, Karol Desnos, Mickaël Dardaillon, Jean-François Nezan
A Fast Heuristic to Pipeline SDF Graphs. SAMOS (2020)
Hugo Miomandre, Jean-François Nezan, Daniel Ménard, Adam Campbell, Anthony Griffin, Seth Hall, Andrew Ensor
Approximate Buffers for Reducing Memory Requirements: Case Study on SKA. SiPS (2020)
Ahmed Kammoun, Wassim Hamidouche, Pierrick Philippe, Olivier Déforges, Fatma Belghith, Nouri Masmoudi, Jean-François Nezan
Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard. IEEE Trans. Circuits Syst. Video Technol. 30 (11) (2020)
Alexandre Honorat, Karol Desnos, Shuvra S. Bhattacharyya, Jean-François Nezan
Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time Constraints. RTNS (2020)
Alexandre Honorat, Karol Desnos, Maxime Pelcat, Jean-François Nezan
Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs. SAMOS (2019)
Ahmed Kammoun, Wassim Hamidouche, Pierrick Philippe, Fatma Belghith, Nouri Massmoudi, Jean-François Nezan
Hardware Acceleration of Approximate Transform Module for the Versatile Video Coding Standard. EUSIPCO (2019)
Ahmed Kammoun, Wassim Hamidouche, Fatma Belghith, Jean-François Nezan, Nouri Masmoudi
Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard. IEEE Trans. Consumer Electron. 64 (4) (2018)
Maxime Pelcat, Alexandre Mercat, Karol Desnos, Luca Maggiani, Yanzhou Liu, Julien Heulot, Jean-François Nezan, Wassim Hamidouche, Daniel Ménard, Shuvra S. Bhattacharyya
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Ahmed Kammoun, S. Ben Jdidia, Fatma Belghith, Wassim Hamidouche, Jean-François Nezan, Nouri Masmoudi
An optimized hardware implementation of 4-point adaptive multiple transform design for post-HEVC. ATSIP (2018)
Nicolas Sourbier, Jean-François Nezan, Cyril Tasse, Julien Hascoet
Optimization of Calibration Algorithms on a Manycore Embedded Platform. SiPS (2018)
Julien Hascoet, Benoît Dupont de Dinechin, Karol Desnos, Jean-François Nezan
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore. HPEC (2018)
Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. PARMA-DITAM@HiPEAC (2018)
Hamza Deroui, Karol Desnos, Jean-François Nezan, Alix Munier Kordon
Relaxed subgraph execution model for the throughput evaluation of IBSDF graphs. SAMOS (2017)
Hamza Deroui, Karol Desnos, Jean-François Nezan, Alix Munier Kordon
Throughput evaluation of DSP applications based on hierarchical dataflow models. ISCAS (2017)
Judicael Menant, Guillaume Gautier, Muriel Pressigout, Luce Morin, Jean-François Nezan
An automatized method to parameterize embedded stereo matching algorithms. J. Syst. Archit. 80 (2017)
Anas Jallouli, Fatma Belghith, Mohamed Ali Ben Ayed, Wassim Hamidouche, Jean-François Nezan, Nouri Masmoudi
Statistical analysis of Post-HEVC encoded videos. SiPS (2017)
Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin
Hierarchical Dataflow Model for efficient programming of clustered manycore processors. ASAP (2017)
Judicaël Menant, Jean-François Nezan, Luce Morin, Muriel Pressigout
A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform. 3D Image Processing, Measurement (3DIPM), and Applications (2017)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
On Memory Reuse Between Inputs and Outputs of Dataflow Actors. ACM Trans. Embed. Comput. Syst. 15 (2) (2016)
Trevor Gee, Patrice Delmas, Sylvain Joly, Valentin Baron, Rachel Ababou, Jean-François Nezan
A dedicated lightweight binocular stereo system for real-time depth-map generation. DASIP (2016)
Zheng Zhou, William Plishker, Shuvra S. Bhattacharyya, Karol Desnos, Maxime Pelcat, Jean-François Nezan
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing. J. Signal Process. Syst. 83 (3) (2016)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Distributed Memory Allocation Technique for Synchronous Dataflow Graphs. SiPS (2016)
Jean-François Nezan, Alexandre Mercat, Patrice Delmas, Georgy L. Gimel'farb
Optimized Belief Propagation Algorithm onto Embedded Multi and Many-Core Systems for Stereo Matching. PDP (2016)
Judicael Menant, Guillaume Gautier, Jean-François Nezan, Muriel Pressigout, Luce Morin
A comparison of cost construction methods onto a C6678 platform for stereo matching. DASIP (2016)
Maxime Pelcat, Karol Desnos, Luca Maggiani, Yanzhou Liu, Julien Heulot, Jean-François Nezan, Shuvra S. Bhattacharyya
Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems. SiPS (2016)
Julien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin
Implementation of a Fast Fourier transform algorithm onto a manycore processor. DASIP (2015)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications. ICASSP (2015)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application. J. Signal Process. Syst. 80 (1) (2015)
Judicael Menant, Muriel Pressigout, Luce Morin, Jean-François Nezan
Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP. DASIP (2014)
Julien Heulot, Maxime Pelcat, Jean-François Nezan, Yaset Oliva, Slaheddine Aridhi, Shuvra S. Bhattacharyya
Just-in-time scheduling techniques for multicore signal processing systems. GlobalSIP (2014)
Alexandre Mercat, Jean-François Nezan, Daniel Ménard, Jinglin Zhang
Implementation of a Stereo Matching algorithm onto a Manycore Embedded System. ISCAS (2014)
Julien Heulot, Judicael Menant, Maxime Pelcat, Jean-François Nezan, Luce Morin, Muriel Pressigout, Slaheddine Aridhi
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application. DASIP (2014)
Zheng Zhou, Karol Desnos, Maxime Pelcat, Jean-François Nezan, William Plishker, Shuvra S. Bhattacharyya
Scheduling of parallelized synchronous dataflow actors. ISSoC (2013)
Julien Heulot, Jani Boutellier, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors. AHS (2013)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Shuvra S. Bhattacharyya, Slaheddine Aridhi
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration. ICSAMOS (2013)
Jinglin Zhang, Jean-François Nezan, Maxime Pelcat, Jean-Gabriel Cousin
Real-time GPU-based local stereo matching method. DASIP (2013)
Julien Heulot, Karol Desnos, Jean-François Nezan, Maxime Pelcat, Mickaël Raulet, Hervé Yviquel, P.-L. Lagalaye, Jean-Christophe Le Lann
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC. DASIP (2012)
Jinglin Zhang, Jean-François Nezan, Jean-Gabriel Cousin, Erwan Raffin
Implementation of stereo matching using a high level compiler for parallel computing acceleration. IVCNZ (2012)
Jinglin Zhang, Jean-François Nezan, Jean-Gabriel Cousin
Implementation of Motion Estimation Based on Heterogeneous Parallel Computing System with OpenCL. HPCC-ICESS (2012)
Manel Hentati, Yassine Aoudni, Jean-François Nezan, Mohamed Abid
A hierarchical implementation of Hadamard transform using RVC-CAL dataflow programming and dynamic partial reconfiguration. DASIP (2012)
Manel Hentati, Samya Elaoud, Yassine Aoudni, Jean-François Nezan, Mohamed Abid
An efficient Resource Management to optimize the placement of hardware task on FPGA in the RVC framework. Des. Autom. Embed. Syst. 16 (4) (2012)
Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph. ICSAMOS (2012)
Jean-François Nezan, Nicolas Siret, Matthieu Wipliez, Francesca Palumbo, Luigi Raffo
Multi-purpose systems: A novel dataflow-based generation and mapping strategy. ISCAS (2012)
Nicolas Siret, Jean-François Nezan, Aimad Rhatay
Design of a processor optimized for syntax parsing in video decoders. DASIP (2011)
Yaset Oliva, Maxime Pelcat, Jean-François Nezan, Jean-Christophe Prévotet, Slaheddine Aridhi
Building a RTOS for MPSoC dataflow programming. SoC (2011)
Matthieu Wipliez, Ghislain Roquier, Jean-François Nezan
Software Code Generation for the RVC-CAL Language. J. Signal Process. Syst. 63 (2) (2011)
Manel Hentati, Yassine Aoudni, Jean-François Nezan, Mohamed Abid, Olivier Déforges
FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study. DASIP (2011)
Pengcheng Mu, Jean-François Nezan, Mickaël Raulet, Jean-Gabriel Cousin
Advanced list scheduling heuristic for task scheduling with communication contention for parallel embedded systems. Sci. China Inf. Sci. 53 (11) (2010)
Nicolas Siret, Matthieu Wipliez, Jean-François Nezan, Aimad Rhatay
Hardware code generation from dataflow programs. DASIP (2010)
Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi
Adaptive multicore scheduling for the LTE uplink. AHS (2010)
Marcus Barkowsky, Médéric Blestel, Mathieu Carnec, Adlen Ksentini, Patrick Le Callet, Gérard Madec, Raoul Monnier, Jean-François Nezan, Romuald Pépion, Yohann Pitrey, Jean-François Travers, Mickaël Raulet, Alain Untersee
Overview of the SVC4QoE Project. MobiMedia (2010)
Nicolas Siret, Ismaïl Sabry, Jean-François Nezan, Mickaël Raulet
A codesign synthesis from an MPEG-4 decoder dataflow description. ISCAS (2010)
Maxime Pelcat, Jonathan Piat, Matthieu Wipliez, Slaheddine Aridhi, Jean-François Nezan
An Open Framework for Rapid Prototyping of Signal Processing Applications. EURASIP J. Embed. Syst. 2009 (2009)
Fabrice Urban, Jean-François Nezan, Mickaël Raulet
HDS, a real-time multi-DSP motion estimator for MPEG-4 H.264 AVC high definition video encoding. J. Real Time Image Process. 4 (1) (2009)
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi, Jean-François Nezan
Scalable compile-time scheduler for multi-core architectures. DATE (2009)
Ihab Amer, Christophe Lucarz, Ghislain Roquier, Marco Mattavelli, Mickaël Raulet, Jean-François Nezan, Olivier Déforges
Reconfigurable video coding on multicore. IEEE Signal Process. Mag. 26 (6) (2009)
Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, Olivier Déforges
A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 18 (12) (2008)
Ghislain Roquier, Matthieu Wipliez, Mickaël Raulet, Jean-François Nezan, Olivier Déforges
Software synthesis of CAL actors for the MPEG reconfigurable Video Coding framework. ICIP (2008)
Maxime Pelcat, Slaheddine Aridhi, Jean-François Nezan
Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm CoRR (2008)
Matthieu Wipliez, Ghislain Roquier, Mickaël Raulet, Jean-François Nezan, Olivier Déforges
Code generation for the MPEG Reconfigurable Video Coding framework: From CAL actions to C functions. ICME (2008)
Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, Olivier Déforges
H.264 fractional motion estimation refinement: A real-time and low complexity hardware solution forhd sequences. EUSIPCO (2007)
Pengcheng Mu, Mickaël Raulet, Jean-François Nezan, Jean-Gabriel Cousin
Automatic code generation for multi-microblaze system with syndex. EUSIPCO (2007)
Ghislain Roquier, Mickaël Raulet, Jean-François Nezan, Olivier Déforges
Using RTOS in the AAA methodology automatic executive generation. EUSIPCO (2006)
Fabrice Urban, Mickaël Raulet, Jean-François Nezan, Olivier Déforges
Automatic dsp cache memory management and fast prototyping for multiprocessor image applications. EUSIPCO (2006)
Mickaël Raulet, Fabrice Urban, Jean-François Nezan, Christophe Moy, Olivier Déforges, Yves Sorel
Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link. EURASIP J. Adv. Signal Process. 2006 (2006)
Markus Rupp, Thomas Kaiser, Jean-François Nezan, Gerhard Schmidt
Signal Processing with High Complexity: Prototyping and Industrial Design. EURASIP J. Embed. Syst. 2006 (2006)
Mickaël Raulet, Christophe Moy, Fabrice Urban, Jean-François Nezan, Olivier Déforges
SynDEx executive kernels for fast developments of applications over heterogeneous architectures. EUSIPCO (2005)
Jean-François Nezan, Olivier Déforges, Mickaël Raulet
Fast Prototyping Methodology for Distributed and Heterogeneous Architectures: Application to Mpeg-4 Video Tools. Des. Autom. Embed. Syst. 9 (2) (2004)
Nicolas Ventroux, Jean-François Nezan, Mickaël Raulet, Olivier Déforges
Rapid prototyping for an optimized MPEG4 decoder implementation over a parallel heterogeneous architecture. ICME (2003)
Nicolas Ventroux, Jean-François Nezan, Mickaël Raulet, Olivier Déforges
Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogenous architecture. ICASSP (2) (2003)
Yann Le Mener, Mickaël Raulet, Jean-François Nezan, Apostolos A. Kountouris, Christophe Moy
Syndex executive kernel development for DSPs TI C6X applied to real-time and embedded multiprocessors architectures. EUSIPCO (2002)
Jean-François Nezan, Olivier Déforges, Mickaël Raulet
Rapid prototyping methodology for multi-DSP TI C6X platforms applied to an Mpeg-2 coding application. SPAA (2002)
Jean-François Nezan, Virginie Fresse, Olivier Déforges, Mickaël Raulet
A VsynDEx Methodology for Fast Prototyping of Multi-C6x DSP Architectures. PDPTA (2002)
Virginie Fresse, Olivier Déforges, Jean-François Nezan
AVSynDEx: A Rapid Prototyping Process Dedicated to the Implementation of Digital Image Processing Applications on Multi-DSP and FPGA Architectures. EURASIP J. Adv. Signal Process. 2002 (9) (2002)