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AISTECS@HiPEAC
2016
2017
2018
2016
2018
Keyphrases
Publications
2018
Dimitris Syrivelis
,
Andrea Reale
,
Kostas Katrinis
,
Christian Pinto
A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing.
AISTECS@HiPEAC
(2018)
Giovanna Calò
,
Gaetano Bellanca
,
Ali Emre Kaplan
,
Franco Fuschini
,
Marina Barbiroli
,
Michele Bozzetti
,
Paolo Bassi
,
Vincenzo Petruzzelli
Integrated Vivaldi antennas, an enabling technology for optical wireless networks on chip.
AISTECS@HiPEAC
(2018)
Amir Atabaki
Monolithic Optical Interconnects in Zero-Change CMOS.
AISTECS@HiPEAC
(2018)
Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS 2018, Manchester, United Kingdom, January 22-22, 2018
AISTECS@HiPEAC
(2018)
Brian Lebiednik
,
Sergi Abadal
,
Hyoukjun Kwon
,
Tushar Krishna
Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip.
AISTECS@HiPEAC
(2018)
2017
Kari Clark
,
Phill Watt
Enabling high performance rack-scale optical switching through global synchronisation.
AISTECS@HiPEAC
(2017)
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017
AISTECS@HiPEAC
(2017)
Jeremiah J. Wilke
Bringing minimal routing back to HPC through silicon photonics: a study of "flexfly" architectures with the structural simulation toolkit (SST).
AISTECS@HiPEAC
(2017)
Benoît Dupont de Dinechin
,
Amaury Graillat
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor.
AISTECS@HiPEAC
(2017)
Syed Ijlal Shah
Interconnects for next generation SoC designs.
AISTECS@HiPEAC
(2017)
Emmanuel Ofori-Attah
,
Michael Opoku Agyeman
A survey of low power NoC design techniques.
AISTECS@HiPEAC
(2017)
Muhammad Obaidullah
,
Gul N. Khan
Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology.
AISTECS@HiPEAC
(2017)
Fernando Pereñíguez-Garcia
,
José L. Abellán
Secure communications in wireless network-on-chips.
AISTECS@HiPEAC
(2017)
Monobrata Debnath
,
Dimitris Konstantinou
,
Chrysostomos Nicopoulos
,
Giorgos Dimitrakopoulos
,
Wei-Ming Lin
,
Junghee Lee
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
AISTECS@HiPEAC
(2017)
Marco Balboni
,
Davide Bertozzi
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.
AISTECS@HiPEAC
(2017)
Jean-Pierre Panziera
BXI: designing a network for eXascale.
AISTECS@HiPEAC
(2017)
François Abel
,
Andreas Doering
Microserver + micro-switch = micro-datacenter.
AISTECS@HiPEAC
(2017)
Nikos Pleros
,
Nikos Terzenidis
,
Theoni Alexoudi
,
K. Vyrsokinos
,
George T. Kanellos
,
Dimitris Syrivelis
Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing.
AISTECS@HiPEAC
(2017)
Yong Hu
,
Daniel Müller-Gritschneder
,
Ulf Schlichtmann
Model-based framework for networks-on-chip design space exploration.
AISTECS@HiPEAC
(2017)
2016
Gabriele Miorandi
,
Mahdi Tala
,
Marco Balboni
,
Luca Ramini
,
Davide Bertozzi
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems.
AISTECS@HiPEAC
(2016)
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016
AISTECS@HiPEAC
(2016)
Muhammad Ridwan Madarbux
,
Anouk Van Laer
,
Philip M. Watts
,
Timothy M. Jones
Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems.
AISTECS@HiPEAC
(2016)
Armin Runge
,
Reiner Kolla
Consideration of the Flit Size for Deflection Routing based Network-on-Chips.
AISTECS@HiPEAC
(2016)
Sébastien Rumley
,
Meisam Bahadori
,
Ke Wen
,
Dessislava Nikolova
,
Keren Bergman
PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects.
AISTECS@HiPEAC
(2016)
Rafael K. V. Maeda
,
Peng Yang
,
Xiaowen Wu
,
Zhe Wang
,
Jiang Xu
,
Zhehui Wang
,
Haoran Li
,
Luan H. K. Duong
,
Zhifei Wang
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
AISTECS@HiPEAC
(2016)
Najwa Salama
,
Azeddien M. Sllame
Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems.
AISTECS@HiPEAC
(2016)
Nikos Terzenidis
,
Pavlos Maniotis
,
Nikos Pleros
Bringing OptoBoards to HPC-scale environments: An OptoHPC simulation engine.
AISTECS@HiPEAC
(2016)
Robert Hesse
,
Natalie D. Enright Jerger
Hierarchical Clustering for On-Chip Networks.
AISTECS@HiPEAC
(2016)