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Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling.
Sascha Uhrig
S. Maier
Georgi Kuzmanov
Theo Ungerer
Published in:
IPDPS (2006)
Keyphrases
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reconfigurable architecture
processor core
systolic array
ibm zenterprise
data processing
multi user
management system
resource allocation
input output