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David Trilla
ORCID
Publication Activity (10 Years)
Years Active: 2016-2021
Publications (10 Years): 12
Top Topics
Real Time Database Systems
Energy Consumption
Architectural Model
Prefetching
Top Venues
IOLTS
DSD
MICRO
ETS
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Publications
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David Trilla
,
John-David Wellman
,
Alper Buyuktosunoglu
,
Pradip Bose
NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators.
MICRO
(2021)
Francisco Bas
,
Sergi Alcaide
,
Ruben Lorenzo
,
Guillem Cabo
,
Guillermo Gil
,
Oriol Sala
,
Fabio Mazzocchetti
,
David Trilla
,
Jaume Abella
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping.
IOLTS
(2021)
Guillem Cabo
,
Francisco Bas
,
Ruben Lorenzo
,
David Trilla
,
Sergi Alcaide
,
Miquel Moretó
,
Carles Hernández
,
Jaume Abella
SafeSU: an Extended Statistics Unit for Multicore Timing Interference.
ETS
(2021)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices.
IEEE Trans. Sustain. Comput.
6 (3) (2021)
Oriol Sala
,
Sergi Alcaide
,
Guillem Cabo
,
Francisco Bas
,
Ruben Lorenzo
,
Pedro Benedicte
,
David Trilla
,
Guillermo Gil
,
Fabio Mazzocchetti
,
Jaume Abella
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation.
IOLTS
(2021)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation.
DSD
(2019)
David Trilla
,
Francisco J. Cazorla
,
Carles Hernández
,
Jaume Abella
Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors.
IEEE Des. Test
36 (6) (2019)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior.
DSD
(2019)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
Cache side-channel attacks and time-predictability in high-performance critical real-time systems.
DAC
(2018)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
Modelling bus contention during system early design stages.
SIES
(2017)
David Trilla
,
Carles Hernández
,
Jaume Abella
,
Francisco J. Cazorla
Resilient random modulo cache memories for probabilistically-analyzable real-time systems.
IOLTS
(2016)
David Trilla
,
Javier Jalle
,
Mikel Fernández
,
Jaume Abella
,
Francisco J. Cazorla
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.
RTAS
(2016)