Tullio Vardanega

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 31

Top Venues

Publications

Gabriele Pozzan, Costanza Padova, Chiara Montuori, Barbara Arfé, Tullio Vardanega
Experimental Analysis of First-Grade Students' Block-Based Programming Problem Solving Processes. ITiCSE (1) (2024)
Enrico Nardelli, Francesco Lacchia, Renzo Davoli, Michael Lodi, Marco Sbaraglia, Veronica Rossano, Enrichetta Gentile, Violetta Lonati, Mattia Monga, Anna Morpurgo, Luca Forlizzi, Giovanna Melideo, Sara Capecchi, Ilenia Fronza, Tullio Vardanega
Learning Iteration for Grades 2-3: Puzzles vs. UMC in Code.org. SIGCSE (2) (2023)
Marco Aldinucci, Elena Maria Baralis, Valeria Cardellini, Iacopo Colonnelli, Marco Danelutto, Sergio Decherchi, Giuseppe Di Modica, Luca Ferrucci, Marco Gribaudo, Francesco Iannone, Marco Lapegna, Doriana Medic, Giuseppa Muscianisi, Francesca Righetti, Eva Sciacca, Nicola Tonellotto, Mauro Tortonesi, Paolo Trunfio, Tullio Vardanega
A Systematic Mapping Study of Italian Research on Workflows. SC Workshops (2023)
Mattia Bottaro, Tullio Vardanega
Evaluating a multicore Mixed-Criticality System implementation against a temporal isolation kernel. J. Syst. Archit. 130 (2022)
Gabriele Pozzan, Tullio Vardanega
Rafting multiplayer video games. Softw. Pract. Exp. 52 (4) (2022)
Alberto Gutierrez-Torre, Kiyana Bahadori, Shuja Ur Rehman Baig, Waheed Iqbal, Tullio Vardanega, Josep Lluís Berral, David Carrera
Automatic Distributed Deep Learning Using Resource-Constrained Edge Devices. IEEE Internet Things J. 9 (16) (2022)
Dilan Perale, Tullio Vardanega
Removing bias from the judgment day: A Ravenscar-based toolbox for quantitative comparison of EDF-to-RM uniprocessor scheduling. J. Syst. Archit. 119 (2021)
Tullio Vardanega
A new start: Introducing the journal-track proceedings of the 24th Ada-Europe conference on reliable software technologies. J. Syst. Archit. 111 (2020)
Barbara Arfé, Tullio Vardanega, Lucia Ronconi
The effects of coding on children's planning and inhibition skills. Comput. Educ. 148 (2020)
Mirko Bez, Giacomo Fornari, Tullio Vardanega
The Scalability Challenge of Ethereum: An Initial Quantitative Analysis. SOSE (2019)
Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Tullio Vardanega
Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Comput. Surv. 52 (1) (2019)
Tullio Vardanega
A Little Look Outside of the Box. MDE4IoT/ModComp@MoDELS (2019)
Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernández, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. 67 (3) (2018)
Kiyana Bahadori, Tullio Vardanega
Designing and Implementing Elastically Scalable Services - A State-of-the-art Technology Review. CLOSER (2018)
Kiyana Bahadori, Tullio Vardanega
DevOps Meets Dynamic Orchestration. DEVOPS (2018)
Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernández, Tullio Vardanega, Guillem Bernat
Reconciling Time Predictability and Performance in Future Computing Systems. IEEE Des. Test 35 (2) (2018)
Stefano Munari, Sebastiano Valle, Tullio Vardanega
Microservice-Based Agile Architectures: An Opportunity for Specialized Niche Technologies. Ada-Europe (2018)
Tullio Vardanega, Alberto Simioni
In Pursuit of Architectural Agility: Experimenting with Microservices. SCC (2018)
Tullio Vardanega, Monica Fedeli
A two-staged capstone project to foster university-business dialogue. ITiCSE (2018)
Suzana Milutinovic, Enrico Mezzetti, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla
On uses of extreme value theory fit for industrial-quality WCET analysis. SIES (2017)
Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. IEEE Trans. Computers 66 (4) (2017)
Paolo Carletto, Tullio Vardanega
Ravenscar-EDF: Comparative Benchmarking of an EDF Variant of a Ravenscar Runtime. Ada-Europe (2017)
Enrico Mezzetti, Mikel Fernández, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application. RTAS (2017)
Suzana Milutinovic, Jaume Abella, Irune Agirre, Mikel Azkarate-askasua, Enrico Mezzetti, Tullio Vardanega, Francisco J. Cazorla
Software Time Reliability in the Presence of Cache Memories. Ada-Europe (2017)
Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-askasua, Tullio Vardanega, Francisco J. Cazorla
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. WCET (2016)
Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD (2016)
Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla
Measurement-Based Timing Analysis of the AURIX Caches. WCET (2016)
Davide Compagnin, Tullio Vardanega
An automated framework for the timing analysis of applications for an automotive multicore processor. ETFA (2016)
Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernández, Andrea Gianarro, Ian Broster, Francisco J. Cazorla
Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems 47 (2016)
Laura Baracchi, Silvia Mazzini, Stefano Puri, Tullio Vardanega
Lessons Learned in a Journey Toward Correct-by-Construction Model-Based Development. Ada-Europe (2016)
Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla
Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore. SAFECOMP Workshops (2016)
Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. Leibniz Trans. Embed. Syst. 2 (1) (2015)
Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
Resource usage templates and signatures for COTS multicore processors. DAC (2015)
Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. ISORC (2015)
Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla
Timing analysis of an avionics case study on complex hardware/software platforms. DATE (2015)
Marco Ziccardi, Enrico Mezzetti, Tullio Vardanega, Jaume Abella, Francisco J. Cazorla
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis. RTSS (2015)
Irune Agirre, Mikel Azkarate-askasua, Carles Hernández, Jaume Abella, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD (2015)
Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, Tullio Vardanega
Software-enforced Interconnect Arbitration for COTS Multicores. WCET (2015)
Davide Compagnin, Enrico Mezzetti, Tullio Vardanega
Experimental Evaluation of Optimal Schedulers Based on Partitioned Proportionate Fairness. ECRTS (2015)
Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, Tullio Vardanega
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES (2015)
Marco Ziccardi, Martin Schoeberl, Tullio Vardanega
A time-composable operating system for the Patmos processor. SAC (2015)
Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. DAC (2015)
Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
Introduction to partial time composability for COTS multicores. SAC (2015)
Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla
A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning. CIT/IUCC/DASC/PICom (2015)
Valentino Baraldo, Alberto Zuccato, Tullio Vardanega
Reconciling Service Orientation with the Cloud. SOSE (2015)
Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, Francisco J. Cazorla
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. WCET (2014)
Marco Panunzio, Tullio Vardanega
An architectural approach with separation of concerns to address extra-functional requirements in the development of embedded real-time software systems. J. Syst. Archit. 60 (9) (2014)
Marco Panunzio, Tullio Vardanega
A component-based process with separation of concerns for the development of embedded real-time software systems. J. Syst. Softw. 96 (2014)
Jaume Abella, Eduardo Quiñones, Franck Wartel, Tullio Vardanega, Francisco J. Cazorla
Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. ECRTS (2014)
Luca Bonato, Enrico Mezzetti, Tullio Vardanega
Supporting Global Resource Sharing in RUN-scheduled Multiprocessor Systems. RTNS (2014)
Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. DSD (2014)
Andrea Baldovin, Geoffrey Nelissen, Tullio Vardanega, Eduardo Tovar
SPRINT: Extending RUN to Schedule Sporadic Tasks. RTNS (2014)
Davide Compagnin, Enrico Mezzetti, Tullio Vardanega
Putting RUN into Practice: Implementation and Evaluation. ECRTS (2014)
Alberto Zuccato, Tullio Vardanega
Implementing Elastic Capacity in a Service-Oriented PaaS. ESOCC Workshops (2014)
Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery D. Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim
PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12 (2s) (2013)
Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla
Achieving timing composability with measurement-based probabilistic timing analysis. ISORC (2013)
Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega
Towards a Time-Composable Operating System. Ada-Europe (2013)
Silvia Mazzini, John M. Favaro, Tullio Vardanega
Cross-Domain Reuse: Lessons Learned in a Multi-project Trajectory. ICSR (2013)
Franck Wartel, Leonidas Kosmidis, Code Lo, Benoit Triquet, Eduardo Quiñones, Jaume Abella, Adriana Gogonel, Andrea Baldovin, Enrico Mezzetti, Liliana Cucu, Tullio Vardanega, Francisco J. Cazorla
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. SIES (2013)
Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega
Limited preemptive scheduling of non-independent task sets. EMSOFT (2013)
Enrico Mezzetti, Tullio Vardanega
A rapid cache-aware procedure positioning optimization to favor incremental development. IEEE Real-Time and Embedded Technology and Applications Symposium (2013)
Francisco J. Cazorla, Tullio Vardanega, Eduardo Quiñones, Jaume Abella
Upper-bounding Program Execution Time with Extreme Value Theory. WCET (2013)
Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources. WCET (2013)
Andrea Baldovin, Andrea Graziano, Enrico Mezzetti, Tullio Vardanega
Kernel-level time composability for avionics applications. SAC (2013)
Zoë R. Stephenson, Jaume Abella, Tullio Vardanega
Supporting industrial use of probabilistic timing analysis with explicit argumentation. INDIN (2013)
Marco Panunzio, Tullio Vardanega
On Software Reference Architectures and Their Application to the Space Domain. ICSR (2013)
Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega
A Time-composable Operating System. WCET (2012)
Claudio Guidi, Paolo Anedda, Tullio Vardanega
PaaSSOA: An Open PaaS Architecture for Service Oriented Applications. ESOCC (2012)
Patricia López Martínez, Tullio Vardanega
Handling Synchronization Requirements under Separation of Concerns in Model-Driven Component-Based Development. Ada-Europe (2012)
Marco Panunzio, Tullio Vardanega
Ada Ravenscar Code Archetypes for Component-Based Development. Ada-Europe (2012)
Antonio Cicchetti, Federico Ciccozzi, Silvia Mazzini, Stefano Puri, Marco Panunzio, Alessandro Zovi, Tullio Vardanega
CHESS: a model-driven engineering tool environment for aiding the development of complex industrial systems. ASE (2012)
Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzetti, Eduardo Quiñones, Francisco J. Cazorla
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. ECRTS (2012)
Claudio Guidi, Paolo Anedda, Tullio Vardanega
Towards a New Paas Architecture Generation. CLOSER (2012)
Patricia López Martínez, Tullio Vardanega
An MDE approach to address synchronization needs in component-based real-time systems. CBSE (2012)
Marco Panunzio, Tullio Vardanega
Pitfalls and misconceptions in component-oriented approaches for real-time embedded systems: lessons learned and solutions. SIGBED Rev. 8 (1) (2011)
Giovanni Giacobbi, Tullio Vardanega
Measuring I/O Performance in Xen Paravirtualization Virtual Machines. CLOSER (2011)
Marco Panunzio, Tullio Vardanega
A Component Model for On-board Software Applications. EUROMICRO-SEAA (2010)
Enrico Mezzetti, Marco Panunzio, Tullio Vardanega
Preservation of Timing Properties with the Ada Ravenscar Profile. Ada-Europe (2010)
Alessandro Maccagnan, Tullio Vardanega, Erika Feltrin, Giorgio Valle, Mauro Riva, Nicola Cannata
A Multi-Agent System for the Automated Handling of Experimental Protocols in Biological Laboratories. WOA (2010)
Enrico Mezzetti, Tullio Vardanega
Towards a Cache-Aware Development of High Integrity Real-Time Systems. RTCSA (2010)
Daniela Cancila, Roberto Passerone, Tullio Vardanega, Marco Panunzio
Ensuring Correctness in the Specification and Handling of Non-Functional Attributes in High-Integrity Real-Time Embedded Systems. IEEE Trans. Ind. Informatics 6 (2) (2010)
Enrico Mezzetti, Adam Betts, José Ruiz, Tullio Vardanega
Cache-Aware Development of High-Integrity Systems. Ada-Europe (2010)
Enrico Mezzetti, Marco Panunzio, Tullio Vardanega
Bounding the Effects of Resource Access Protocols on Cache Behavior. WCET (2010)
Alessandro Zovi, Tullio Vardanega
Requirements on the Target Programming Language for High-Integrity MDE. Ada-Europe (2009)
Silvia Mazzini, Stefano Puri, Tullio Vardanega
An MDE methodology for the development of high-integrity real-time systems. DATE (2009)
Tullio Vardanega
Property Preservation and Composition with Guarantees: From ASSERT to CHESS. ISORC (2009)
Marco Panunzio, Tullio Vardanega
On Component-Based Development and High-Integrity Real-Time Systems. RTCSA (2009)
Matteo Bordin, Marco Panunzio, Tullio Vardanega
Fitting Schedulability Analysis Theory into Model-Driven Engineering. ECRTS (2008)
Marco Panunzio, Tullio Vardanega
A Metamodel-Driven Process Featuring Advanced Model-Based Timing Analysis. Ada-Europe (2007)
Matteo Bordin, Tullio Vardanega
Real-time Java from an automated code generation perspective. JTRES (2007)
Matteo Bordin, Tullio Vardanega
Correctness by Construction for High-Integrity Real-Time Systems: A Metamodel-Driven Approach. Ada-Europe (2007)
Tullio Vardanega, José F. Ruiz
Introduction. IRTAW (2007)
Marco Panunzio, Tullio Vardanega
An Approach to the Timing Analysis of Hierarchical Systems. RTCSA (2007)
José Antonio Pulido, Juan Antonio de la Puente, Jérôme Hugues, Matteo Bordin, Tullio Vardanega
Ada 2005 code patterns for metamodel-based code generation. IRTAW (2007)
Vaclav Cechticky, Martin Egli, Alessandro Pasetti, O. Rohlik, Tullio Vardanega
A UML2 Profile for Reusable and Verifiable Software Components for Real-Time Applications. ICSR (2006)
José Antonio Pulido, Santiago Urueña, Juan Zamorano, Tullio Vardanega, Juan Antonio de la Puente
Hierarchical Scheduling with Ada 2005. Ada-Europe (2006)
Tullio Vardanega
Property-Preserving Reuse-Geared Approach to Model-Driven Development. RTCSA (2006)
Matteo Bordin, Tullio Vardanega
A New Strategy for the HRT-HOOD to Ada Mapping. Ada-Europe (2005)
Matteo Bordin, Tullio Vardanega
Automated Model-Based Generation of Ravenscar-Compliant Source Code. ECRTS (2005)
Tullio Vardanega, Juan Zamorano, Juan Antonio de la Puente
On the Dynamic Semantics and the Timing Behavior of Ravenscar Kernels. Real Time Syst. 29 (1) (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Tullio Vardanega