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Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.
Alessandro Strano
Carles Hernández
Federico Silla
Davide Bertozzi
Published in:
SoC (2010)
Keyphrases
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design process
low cost
network design
case study
physical design
social networks
modular design
layout design
conceptual model
single chip
circuit design
design methodology
network structure
high speed
neural network
computer aided
process model
vlsi implementation
user interface
chip design