Davide Zoni

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 51

Top Topics

Hardware Implementation

Convolutional Neural Network

Benchmark Suite

Top Venues

Microprocess. Microsystems

Publications

Andrea Galimberti, Michele Piccoli, Davide Zoni
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms. CoRR (2024)
Teo Vallone, Hayri Verner Hasou, Ernesto Colizzi, Sara Vinco, Davide Zoni
A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits. ISQED (2024)
Davide Zoni, Andrea Galimberti, Davide Galli
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research. CoRR (2024)
Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. CoRR (2024)
Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni
A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. DATE (2024)
Andrea Galimberti, Marco Vitali, Sebastiano Vittoria, Davide Zoni
Functional ISS-Driven Verification of Superscalar RISC-V Processors. CoRR (2024)
Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, Emanuele Ruffaldi
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. PARMA-DITAM (2023)
William Fornaciari, Giovanni Agosta, Daniele Cattaneo, Lev Denisov, Andrea Galimberti, Gabriele Magnani, Davide Zoni
Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems. DATE (2023)
William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS (2023)
Andrea Galimberti, Gabriele Montanaro, William Fornaciari, Davide Zoni
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE. PARMA-DITAM (2023)
Davide Zoni, Andrea Galimberti, William Fornaciari
A Survey on Run-time Power Monitors at the Edge. ACM Comput. Surv. 55 (14s) (2023)
Andrea Galimberti, Gabriele Montanaro, Davide Zoni
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs. ICECS (2023)
Andrea Galimberti, Davide Galli, Gabriele Montanaro, William Fornaciari, Davide Zoni
On the use of hardware accelerators in QC-MDPC code-based cryptography. CF (2022)
Gabriele Montanaro, Andrea Galimberti, Ernesto Colizzi, Davide Zoni
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. ICECS 2022 (2022)
Andrea Galimberti, Gabriele Montanaro, William Fornaciari, Davide Zoni
An Evaluation of the State-of-the-Art Software and Hardware Implementations of BIKE. CoRR (2022)
Andrea Galimberti, Davide Galli, Gabriele Montanaro, William Fornaciari, Davide Zoni
FPGA implementation of BIKE for quantum-resistant TLS. DSD (2022)
Davide Zoni, Luca Cremona, William Fornaciari
Design of Side-Channel-Resistant Power Monitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Roberto Ammendola, Yasir Arfat, Olivier Beaumont, Massimo Bernaschi, Andrea Biagioni, Tommaso Boccali, Bérenger Bramas, Carlo Brandolese, Barbara Cantalupo, Mauro Carrozzo, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Iacopo Colonnelli, Paolo Cretaro, Pasqua D'Ambra, Marco Danelutto, Roberto Esposito, Lionel Eyraud-Dubois, Antonio Filgueras, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Brice Goglin, Daniele Gregori, Abdou Guermouche, Francesco Iannone, Michal Kulczewski, Francesca Lo Cicero, Alessandro Lonardo, Alberto Riccardo Martinelli, Michele Martinelli, Xavier Martorell, Giuseppe Massari, Simone Montangero, Gianluca Mittone, Raymond Namyst, Ariel Oleksiak, Paolo Palazzari, Pier Stanislao Paolucci, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Francesco Simula, Federico Terraneo, Samuel Thibault, Massimo Torquati, Matteo Turisini, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach. Microprocess. Microsystems 95 (2022)
Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. 128 (2022)
Andrea Galimberti, Gabriele Montanaro, Davide Zoni
Efficient and Scalable FPGA Design of GF($2^m$2m) Inversion for Post-Quantum Cryptosystems. IEEE Trans. Computers 71 (12) (2022)
Davide Galli, Andrea Galimberti, William Fornaciari, Davide Zoni
On the Effectiveness of True Random Number Generators Implemented on FPGAs. SAMOS (2022)
Davide Zoni, Andrea Galimberti
Cost-effective fixed-point hardware support for RISC-V embedded systems. J. Syst. Archit. 126 (2022)
Gabriele Montanaro, Andrea Galimberti, Ernesto Colizzi, Davide Zoni
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. CoRR (2022)
Luca Cremona, William Fornaciari, Davide Zoni
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems. Sustain. Comput. Informatics Syst. 29 (Part) (2021)
Giovanni Agosta, Daniele Cattaneo, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese, Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo, Massimo Bernaschi, Pasqua D'Ambra, Sergio Saponara, Marco Danelutto, Massimo Torquati, Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto Riccardo Martinelli, Gianluca Mittone, Olivier Beaumont, Bérenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault, Antonio Filgueras, Miquel Vidal, Carlos Álvarez, Xavier Martorell, Ariel Oleksiak, Michal Kulczewski, Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini, Francesco Giacomini, Tommaso Boccali, Simone Montangero, Roberto Ammendola
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale. DSD (2021)
Davide Zoni, Andrea Galimberti, William Fornaciari
An FPU design template to optimize the accuracy-efficiency-area trade-off. Sustain. Comput. Informatics Syst. 29 (Part) (2021)
Davide Zoni, Luca Cremona, William Fornaciari
All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores. IEEE Trans. Computers 69 (5) (2020)
Davide Zoni, Andrea Galimberti, William Fornaciari
Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography. IEEE Access 8 (2020)
Alessandro Barenghi, William Fornaciari, Gerardo Pelosi, Davide Zoni
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (9) (2020)
Alessandro Barenghi, Matteo Brevi, William Fornaciari, Gerardo Pelosi, Davide Zoni
Integrating Side Channel Security in the FPGA Hardware Design Flow. COSADE (2020)
Luca Cremona, William Fornaciari, Andrea Galimberti, Andrea Romanoni, Davide Zoni
VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications. SAMOS (2020)
Davide Zoni, Luca Cremona, William Fornaciari
All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs. IEEE Embed. Syst. Lett. 12 (1) (2020)
Davide Zoni, Andrea Galimberti, William Fornaciari
Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials. IEEE Access 8 (2020)
Davide Zoni
Analysis and countermeasures to side-channel attacks: a hardware design perspective. ReCoSoC (2019)
Alessandro Barenghi, William Fornaciari, Andrea Galimberti, Gerardo Pelosi, Davide Zoni
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions. ICECS (2019)
Tamer Ahmed Eltaras, William Fornaciari, Davide Zoni
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs. PDP (2019)
Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris
Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH (2018)
Giuseppe Massari, Federico Terraneo, Michele Zanella, Davide Zoni
Towards Fine-Grained DVFS in Embedded Multi-core CPUs. ARCS (2018)
Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari
PowerTap: All-digital power meter modeling for run-time power monitoring. Microprocess. Microsystems 63 (2018)
José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61 (2018)
Davide Zoni, Luca Colombo, William Fornaciari
DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks. ACM Trans. Archit. Code Optim. 15 (2) (2018)
Davide Zoni, Luca Cremona, William Fornaciari
PowerProbe: Run-time power modeling through automatic RTL instrumentation. DATE (2018)
Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture. ACM Trans. Design Autom. Electr. Syst. 23 (5) (2018)
William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS (2018)
Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems 51 (2017)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD (2017)
Luca Cremona, William Fornaciari, Andrea Marchese, Michele Zanella, Davide Zoni
DENA: A DVFS-Capable Heterogeneous NoC Architecture. ISVLSI (2017)
Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. 104 (2017)
Davide Zoni, Federico Terraneo, William Fornaciari
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. J. Signal Process. Syst. 83 (3) (2016)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE (2016)
Davide Zoni, Jose Flich, William Fornaciari
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. IEEE Trans. Parallel Distributed Syst. 27 (6) (2016)
Davide Zoni, William Fornaciari
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. ACM J. Emerg. Technol. Comput. Syst. 12 (3) (2015)
Federico Terraneo, Davide Zoni, William Fornaciari
An accurate simulation framework for thermal explorations and optimizations. RAPIDO@HiPEAC (2015)
Davide Zoni, Luca Borghese, Giuseppe Massari, Simone Libutti, William Fornaciari
TEST: Assessing NoC Policies Facing Aging and Leakage Power. DSD (2015)
Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
The MANGO FET-HPC Project: An Overview. CSE (2015)
Davide Zoni, Federico Terraneo, William Fornaciari
A control-based methodology for power-performance optimization in NoCs exploiting DVFS. J. Syst. Archit. 61 (5-6) (2015)
Davide Zoni, William Fornaciari
NBTI-aware design of NoC buffers. INA-OCMC@HiPEAC (2013)
Davide Zoni, William Fornaciari
Sensor-wise methodology to face NBTI stress of NoC buffers. DATE (2013)
Davide Zoni, Federico Terraneo, William Fornaciari
An analytical, dynamic, power-performance router model for run-time NoC optimizations. SoCC (2013)
Federico Terraneo, Davide Zoni, William Fornaciari
A cycle accurate simulation framework for asynchronous NoC design. ISSoC (2013)
Davide Zoni, Jose Flich, William Fornaciari
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. PATMOS (2013)
Simone Corbetta, Davide Zoni, William Fornaciari
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures. ISVLSI (2012)
Andrea Sansottera, Davide Zoni, Paolo Cremonesi, William Fornaciari
Consolidation of multi-tier workloads with performance and reliability constraints. HPCS (2012)
Davide Zoni, Simone Corbetta, William Fornaciari
Thermal/performance trade-off in network-on-chip architectures. ISSoC (2012)
Davide Zoni, William Fornaciari
A sensor-less NBTI mitigation methodology for NoC architectures. SoCC (2012)
Davide Zoni, Patrick Bellasi, William Fornaciari
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures. ARCS (2012)
Davide Zoni, Simone Corbetta, William Fornaciari
HANDS: heterogeneous architectures and networks-on-chip design and simulation. ISLPED (2012)
Carlo Brandolese, William Fornaciari, Luigi Rucco, Davide Zoni
Towards energy-efficient functional configuration in WSNs. PDeS (2012)