Ruben Gran Tejero

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 20

Top Topics

Analytical Model

Parallel Implementation

High Level Synthesis

Learning Experience

Top Venues

J. Syst. Archit.

Publications

Yamilka Toca-Díaz, Reynier Hernández Palacios, Ruben Gran Tejero, Alejandro Valero
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage. Microprocess. Microsystems 106 (2024)
Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. DSD (2023)
Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Diana Göhringer
A cross-platform OpenVX library for FPGA accelerators. J. Syst. Archit. 123 (2022)
Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. 128 (2022)
Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS (2022)
Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. CoRR (2021)
Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
Analytical Model for Memory-Centric High Level Synthesis-Generated Applications. IEEE Trans. Computers 70 (12) (2021)
Juan Segarra, Ruben Gran Tejero, Víctor Viñals
A generic framework to integrate data caches in the WCET analysis of real-time systems. J. Syst. Archit. 120 (2021)
Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez
A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. 156 (2021)
Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Lester Kalms, Diana Göhringer
A Cross-Platform OpenVX Library for FPGA Accelerators. PDP (2021)
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. CoRR (2020)
Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches. IEEE Access 8 (2020)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. IEEE Access 8 (2020)
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. FCCM (2020)
Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. 98 (2019)
Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, José Luis Bosque
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL. J. Supercomput. 75 (3) (2019)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA (2019)
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems. HPCS (2018)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR (2018)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO (2017)
Antonio Vilches, Rafael Asenjo, Angeles G. Navarro, Francisco Corbera, Ruben Gran Tejero, María Jesús Garzarán
Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips. ICCS (2015)
Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems. J. Syst. Archit. 59 (9) (2013)
Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals
A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium (2012)
Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería
On reducing misspeculations in a pipelined scheduler. IPDPS (2009)
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería
An Enhancement for a Scheduling Logic Pipelined over two Cycles . ICCD (2006)