José Luis Briz

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 9

Top Topics

Memory Hierarchy

Top Venues

IEEE Robotics Autom. Lett.

ACM Trans. Embed. Comput. Syst.

Discret. Event Dyn. Syst.

Publications

Laura Elena Rubio Anguiano, José Luis Briz, Antonio Ramírez-Treviño
Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs. IEEE Robotics Autom. Lett. 7 (3) (2022)
Laura Elena Rubio Anguiano, Gaddiel Desirena-Lopez, Antonio Ramírez-Treviño, José Luis Briz
Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN. Discret. Event Dyn. Syst. 29 (3) (2019)
Gaddiel Desirena-Lopez, Antonio Ramírez-Treviño, José Luis Briz, Carlos Renato Vázquez, David Gómez-Gutiérrez
Thermal-aware Real-time Scheduling Using Timed Continuous Petri Nets. ACM Trans. Embed. Comput. Syst. 18 (4) (2019)
Gaddiel Desirena-Lopez, Laura Elena Rubio Anguiano, Antonio Ramírez-Treviño, José Luis Briz
A Flexible Framework for Real-Time Thermal-Aware Schedulers using Timed Continuous Petri Nets. Computación y Sistemas 23 (2) (2019)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA (2019)
Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau
GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Javier Olivito, Javier Resano, José Luis Briz
Accelerating Board Games Through Hardware/Software Codesign. IEEE Trans. Comput. Intell. AI Games 9 (4) (2017)
Gaddiel Desirena-Lopez, Carlos Renato Vázquez, José Luis Briz, Antonio Ramírez-Treviño, David Gómez-Gutiérrez
On-line scheduling in multiprocessor systems based on continuous control using Timed Continuous Petri Nets. WODES (2016)
Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau
Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12 (4) (2016)
Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau
An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED (2013)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism 13 (2011)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Low-Cost Adaptive Data Prefetching. Euro-Par (2008)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35 (4) (2007)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT (2006)
Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals
Software Demand, Hardware Supply. IEEE Micro 26 (4) (2006)
María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP (2001)
Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán
Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing (1998)
José Luis Briz, José Manuel Colom
Implementation of Weighted Place/Transition Nets Based on Linear Enabling Functions. Application and Theory of Petri Nets (1994)