Jose Renau

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 21

Top Topics

Integrated Circuit

Tensor Decomposition

Structural Matching

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau
A Multi-threaded Fast Hardware Compiler for HDLs. CC (2023)
Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO (2021)
David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS (2021)
Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau
LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS (2020)
Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau
LiveHD: A Productive Live Hardware Development Flow. IEEE Micro 40 (4) (2020)
Akash Sridhar, Nursultan Kabylkas, Jose Renau
Load Driven Branch Predictor (LDBP). CoRR (2020)
Rafael Trapani Possignolo, Jose Renau
SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC (2019)
Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau
EMI Architectural Model and Core Hopping. MICRO (2019)
Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau
GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Rafael Trapani Possignolo, Jose Renau
LiveSynth: Towards an Interactive Synthesis Flow. DAC (2017)
Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau
Liam: an actor based programming model for HDLs. MEMOCODE (2017)
Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau
Timing speculative SRAM. ISCAS (2017)
Daphne I. Gorman, Matthew R. Guthaus, Jose Renau
Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO (2017)
Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
Level shifter design for voltage stacking. ISCAS (2017)
Gabriel Southern, Jose Renau
Overhead of deoptimization checks in the V8 javascript engine. IISWC (2016)
Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
SRAM voltage stacking. ISCAS (2016)
Gabriel Southern, Jose Renau
Analysis of PARSEC workload scalability. ISPASS (2016)
Sina Hassani, Gabriel Southern, Jose Renau
LiveSim: Going live with microarchitecture simulation. HPCA (2016)
Rafael Trapani Possignolo, Jose Renau
LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium (2016)
Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD (2016)
Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau
Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12 (4) (2016)
Madan Mohan Das, Gabriel Southern, Jose Renau
Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Madan Mohan Das, Gabriel Southern, Jose Renau
Section based program analysis to reduce overhead of detecting unsynchronized thread communication. PPOPP (2015)
Jose Renau
Message from the program chair. ISPASS (2015)
Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Ehsan K. Ardestani, Jose Renau
ESESC: A fast multicore simulator using Time-Based Sampling. HPCA (2013)
Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau
An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED (2013)
Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau
ESESC: A fast performance, power, and temperature multicore simulator. Hot Chips Symposium (2013)
Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, Jose Renau
Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau
Thermal-aware sampling in architectural simulation. ISLPED (2012)
Michael Brown, Jose Renau
ReRack: power simulation for data centers with renewable energy generation. SIGMETRICS Perform. Evaluation Rev. 39 (3) (2011)
Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau
Releasing efficient beta cores to market early. ISCA (2011)
Jose Renau, Will Eatherton
Hot Chips 22. IEEE Micro 31 (2) (2011)
Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau
A design time simulator for computer architects. ISQED (2011)
Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau
Characterizing processor thermal behavior. ASPLOS (2010)
Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau
Measuring and modeling variabilityusing low-cost FPGAs. FPGA (2009)
Joseph Nayfach-Battilana, Jose Renau
SOI, interconnect, package, and mainboard thermal characterization. ISLPED (2009)
Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau
Measuring power and temperature from real processors. IPDPS (2008)
Sangeetha Sudhakrishnan, Liying Su, Jose Renau
Processor Verification with hwBugHunt. ISQED (2008)
Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau
Understanding bug fix patterns in verilog. MSR (2008)
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau
Estimating design time for system circuits. VLSI-SoC (2007)
Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau
Power model validation through thermal measurements. ISCA (2007)
Francisco J. Mesa-Martinez, Jose Renau
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. MICRO (2007)
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
System and Procesor Design Effort Estimation. VLSI-SoC (Selected Papers) (2007)
Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau
Measuring performance, power, and temperature from real processors. Experimental Computer Science (2007)
Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. 3 (2) (2006)
Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
POSH: a TLS compiler that exploits program structure. PPOPP (2006)
Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau
SEED: scalable, efficient enforcement of dependences. PACT (2006)
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
Energy-Efficient Thread-Level Speculation. IEEE Micro 26 (1) (2006)
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
Thread-Level Speculation on a CMP can be energy efficient. ICS (2005)
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
uComplexity: Estimating Processor Design Effort. MICRO (2005)
Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS (2005)
Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. 3 (2004)
Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
Programming the FlexRAM parallel intelligent memory system. PPOPP (2003)
Michael C. Huang, Jose Renau, Josep Torrellas
Positional Adaptation of Processors: Application to Energy Reduction. ISCA (2003)
José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO (2002)
Michael C. Huang, Jose Renau, Josep Torrellas
Energy-efficient hybrid wakeup logic. ISLPED (2002)
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism 3 (2001)
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
L1 data cache decomposition for energy efficiency. ISLPED (2001)
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems (2000)
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
A framework for dynamic energy efficiency and temperature management. MICRO (2000)