Roger Espasa

Publication Activity (10 Years)

Years Active: 1995-2021
Publications (10 Years): 1

Top Topics

Tensor Decomposition

Application Specific Integrated Circuits

Single Processor

Top Venues

Publications

David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS (2021)
Roger Espasa
Larrabee: A Many-Core Intel Architecture for Visual Computing. HiPEAC (2010)
Jordi Roca, Victor Moya Del Barrio, Carlos González, Vicente Escandell, Albert Murciego, Agustín Fernández, Roger Espasa
A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization. Vis. Comput. 26 (6-8) (2010)
Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan
Larrabee: A Many-Core x86 Architecture for Visual Computing. IEEE Micro 29 (1) (2009)
Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan
Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. 27 (3) (2008)
Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustín Fernández, Roger Espasa
Workload Characterization of 3D Games. IISWC (2006)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. ISPASS (2006)
André Seznec, Roger Espasa
Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers 54 (7) (2005)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
Shader Performance Analysis on a Modern GPU Architecture. MICRO (2005)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. HiPEAC (2005)
Manel Fernández, Roger Espasa
Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. Interaction between Compilers and Computer Architectures (2004)
Manel Fernández, Roger Espasa
Link-Time Path-Sensitive Memory Redundancy Elimination. HPCA (2004)
Manel Fernández, Roger Espasa, Saumya K. Debray
Load redundancy elimination on executable code. Concurr. Comput. Pract. Exp. 15 (10) (2003)
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Theory Comput. Syst. 36 (5) (2003)
Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
Tarantula: A Vector Extension to the Alpha Architecture. ISCA (2002)
Jesús Corbal, Roger Espasa, Mateo Valero
Three-dimensional memory vectorization for high bandwidth media memory systems. MICRO (2002)
Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
Asim: A Performance Model Framework. Computer 35 (2) (2002)
Manel Fernández, Roger Espasa
Speculative Alias Analysis for Executable Code. IEEE PACT (2002)
Manel Fernández, Roger Espasa, Saumya K. Debray
Load Redundancy Elimination on Executable Code. Euro-Par (2001)
Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par (2001)
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
A cost effective architecture for vectorizable numerical and multimedia applications. SPAA (2001)
Jesús Corbal, Roger Espasa, Mateo Valero
On the Efficiency of Reductions in µ-SIMD Media Extensions. IEEE PACT (2001)
Jesús Corbal, Roger Espasa, Mateo Valero
DLP + TLP Processors for the Next Generation of Media Workloads. HPCA (2001)
Jesús Corbal, Roger Espasa, Mateo Valero
Exploiting a New Level of DLP in Multimedia Applications. MICRO (1999)
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
Adding a vector unit to a superscalar processor. International Conference on Supercomputing (1999)
Jesús Corbal, Roger Espasa, Mateo Valero
MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. SC (1999)
Roger Espasa, Mateo Valero
A Simulation Study of Decoupled Vector Architectures. J. Supercomput. 14 (2) (1999)
Roger Espasa, Mateo Valero, James E. Smith
Vector Architectures: Past, Present and Future. International Conference on Supercomputing (1998)
Jesús Corbal, Roger Espasa, Mateo Valero
Command Vector Memory Systems: High Performance at Low Cost. IEEE PACT (1998)
Luis Villa, Roger Espasa, Mateo Valero
A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing (1998)
Luis Villa, Roger Espasa, Mateo Valero
Effective usage of vector registers in decoupled vector architectures. PDP (1998)
Luis Villa, Roger Espasa, Mateo Valero
Registers Size Influence on Vector Architectures. VECPAR (1998)
Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. MICRO (1998)
Francisca Quintana, Roger Espasa, Mateo Valero
An ISA Comparison Between Superscalar and Vector Processors. VECPAR (1998)
Francisca Quintana, Roger Espasa, Mateo Valero
A case for merging the ILP and DLP paradigms. PDP (1998)
Roger Espasa, Mateo Valero
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. HiPC (1997)
Roger Espasa, Mateo Valero
A Victim Cache for Vector Registers. International Conference on Supercomputing (1997)
Roger Espasa, Mateo Valero, James E. Smith
Out-of-Order Vector Architectures. MICRO (1997)
Luis Villa, Roger Espasa, Mateo Valero
Effective Usage of Vector Registers in Advanced Vector Architectures. IEEE PACT (1997)
Roger Espasa, Mateo Valero
Multithreaded Vector Architectures. HPCA (1997)
Roger Espasa, Mateo Valero
Exploiting instruction- and data-level parallelism. IEEE Micro 17 (5) (1997)
Roger Espasa, Mateo Valero
Decoupled Vector Architectures. HPCA (1996)
Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé
Quantitative analysis of vector code. PDP (1995)