Agustín Fernández

Publication Activity (10 Years)

Years Active: 1991-2015
Publications (10 Years): 1

Top Topics

Parameter Space

Retrieval Systems

Higher Dimensional

Top Venues

Publications

Norma Montealegre, David Merodio, Agustín Fernández, Philippe Armbruster
In-flight reconfigurable FPGA-based space systems. AHS (2015)
David López, Josep-Llorenc Cruz, Fermín Sánchez, Agustín Fernández
A take-home exam to assess professional skills. FIE (2011)
Jordi Roca, Victor Moya Del Barrio, Carlos González, Vicente Escandell, Albert Murciego, Agustín Fernández, Roger Espasa
A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization. Vis. Comput. 26 (6-8) (2010)
Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustín Fernández, Roger Espasa
Workload Characterization of 3D Games. IISWC (2006)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. ISPASS (2006)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
Shader Performance Analysis on a Modern GPU Architecture. MICRO (2005)
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. HiPEAC (2005)
Marta Jiménez, José M. Llabería, Agustín Fernández
A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distributed Syst. 14 (10) (2003)
Marta Jiménez, José M. Llabería, Agustín Fernández
Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. 24 (4) (2002)
Marta Jiménez, José M. Llabería, Agustín Fernández
On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA (2000)
Marta Jiménez, José M. Llabería, Agustín Fernández
Performance Evaluation of Tiling for the Register Level. HPCA (1998)
Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
A General Algorithm for Tiling the Register Level. International Conference on Supercomputing (1998)
Marta Jiménez, José María Llabería, Agustín Fernández
Loop bounds computation for multilevel tiling. PDP (1998)
Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I (1996)
Agustín Fernández, José M. Llabería, Miguel Valero-García
Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distributed Syst. 6 (8) (1995)
Alvaro Suárez, José M. Llabería, Agustín Fernández
Scheduling partitions in systolic algorithms. ASAP (1992)
Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
Transformation of systolic algorithms for interleaving partitions. ASAP (1991)
Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC (1991)
Agustín Fernández, José María Llabería, Juan J. Navarro, Miguel Valero-García
Performance evaluation of transputer systems with linear algebra problems. Microprocessing and Microprogramming 32 (1-5) (1991)