José M. Llabería

Publication Activity (10 Years)

Years Active: 1985-2022
Publications (10 Years): 4

Top Topics

Multicore Processors

Top Venues

J. Parallel Distributed Comput.

J. Supercomput.

Publications

Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR (2022)
Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR (2022)
Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77 (10) (2021)
Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125 (2019)
Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería
The reuse cache: downsizing the shared last-level cache. MICRO (2013)
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
Filtering directory lookups in CMPs. Microprocess. Microsystems 35 (8) (2011)
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
Filtering Directory Lookups in CMPs. DSD (2010)
Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería
Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par (2006)
Marta Jiménez, José M. Llabería, Agustín Fernández
A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distributed Syst. 14 (10) (2003)
Marta Jiménez, José M. Llabería, Agustín Fernández
Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. 24 (4) (2002)
Marta Jiménez, José M. Llabería, Agustín Fernández
On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA (2000)
Enric Morancho, José M. Llabería, Àngel Olivé
Two-Level Address Storage and Address Prediction (Research Note). Euro-Par (2000)
Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería
Modeling load address behaviour through recurrences. ISPASS (2000)
Anna M. del Corral, José M. Llabería
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. IEEE Trans. Computers 48 (4) (1999)
Enric Morancho, José M. Llabería, Àngel Olivé
Looking at History to Filter Allocations in Prediction Tables. IEEE PACT (1999)
Marta Jiménez, José M. Llabería, Agustín Fernández
Performance Evaluation of Tiling for the Register Level. HPCA (1998)
Enric Morancho, José M. Llabería, Àngel Olivé
Split Last-Address Predictor. IEEE PACT (1998)
Anna M. del Corral, José M. Llabería
New Access Order to Reduce Inter-Vector-Conflicts. VECPAR (1998)
Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
A General Algorithm for Tiling the Register Level. International Conference on Supercomputing (1998)
Anna M. del Corral, José M. Llabería
Reducing Inter-Vector-Conflicts in Complex Memory Systems. International Conference on Supercomputing (1996)
Anna M. del Corral, José M. Llabería
Increasing the Effective Memory Bandwidth in Multivector Processors. EUROMICRO (1996)
Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I (1996)
Anna M. del Corral, José M. Llabería
Access order to avoid inter-vector-conflicts in complex memory systems. IPPS (1995)
Agustín Fernández, José M. Llabería, Miguel Valero-García
Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distributed Syst. 6 (8) (1995)
Anna M. del Corral, José M. Llabería
Out-of-order access to vector elements in order to reduce conflicts in vector processors. SPDP (1994)
Antonio González, José M. Llabería
Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers 42 (3) (1993)
Jordi Cortadella, José M. Llabería
Evaluation of A + B = K Conditions Without Carry Propagation. IEEE Trans. Computers 41 (11) (1992)
Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro
Increasing the Number of Strides for Conflict-Free Vector Access. ISCA (1992)
Alvaro Suárez, José M. Llabería, Agustín Fernández
Scheduling partitions in systolic algorithms. ASAP (1992)
Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero
On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC (1991)
Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
Transformation of systolic algorithms for interleaving partitions. ASAP (1991)
Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC (1991)
Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería
Balanced Loop Partitioning Using GTS. LCPC (1991)
Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
Implementation of systolic algorithms using pipelined functional units. ASAP (1990)
Antonio González, José M. Llabería
Instruction fetch unit for parallel execution of branch instructions. ICS (1989)
Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
Systematic Hardware Adaptation of Systolic Algorithms. ISCA (1989)
Juan J. Navarro, José M. Llabería, Mateo Valero
Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. Computer 20 (7) (1987)
Juan J. Navarro, José M. Llabería, Mateo Valero
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP (1986)
Juan J. Navarro, José M. Llabería, Mateo Valero
Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA (1986)
José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA (1985)