Teresa Monreal

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 8

Top Topics

Spatial Locality

Compression Algorithm

Top Venues

DroneSE/RAPIDO@HiPEAC

J. Parallel Distributed Comput.

Publications

Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matias, Luis Pinuel, Teresa Monreal, José María Llabería
Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR (2024)
Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA (2023)
Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS (2023)
Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR (2022)
Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR (2022)
Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC (2022)
Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77 (10) (2021)
Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125 (2019)
Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals
Light NUCA: A proposal for bridging the inter-cache latency gap. DATE (2009)
Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD (2008)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
Microarchitectural Support for Speculative Register Renaming. IPDPS (2007)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
Speculative early register release. Conf. Computing Frontiers (2006)
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3 (2/3) (2005)
Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53 (10) (2004)
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
Hardware Schemes for Early Register Release. ICPP (2002)
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000)
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO (1999)