Víctor Viñals

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 17

Top Topics

Gigabit Ethernet

Spatial Locality

Optical Networks

Top Venues

J. Syst. Archit.

J. Parallel Distributed Comput.

Publications

Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matias, Luis Pinuel, Teresa Monreal, José María Llabería
Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR (2024)
Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA (2023)
Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS (2023)
Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR (2022)
Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR (2022)
Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC (2022)
Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS (2022)
Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77 (10) (2021)
Juan Segarra, Ruben Gran Tejero, Víctor Viñals
A generic framework to integrate data caches in the WCET analysis of real-time systems. J. Syst. Archit. 120 (2021)
Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, Oscar G. Plata
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. DCC (2019)
Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125 (2019)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA (2019)
Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61 (6) (2018)
Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. J. Parallel Distributed Comput. 95 (2016)
Marta Ortín, Luca Ramini, Marco Balboni, Lorenzo Zuolo, Maddalena Nonato, Víctor Viñals, Davide Bertozzi
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization. SiPhotonics@HiPEAC (2015)
Juan Segarra, Clemente Rodríguez, Ruben Gran, Luis C. Aparicio, Víctor Viñals
ACDC: Small, Predictable and High-Performance Data Cache. ACM Trans. Embed. Comput. Syst. 14 (2) (2015)
Ruben Gran, Juan Segarra, A. Pedro-Zapater, Luis C. Aparicio, Víctor Viñals, Clemente Rodríguez
A predictable hardware to exploit temporal reuse in real-time and embedded systems. J. Syst. Archit. 61 (5-6) (2015)
Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD (2014)
Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
Dynamic construction of circuits for reactive traffic in homogeneous CMPs. DATE (2014)
Marco Balboni, Marta Ortín-Obón, Alessandro Capotondi, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Luca Ramini, Víctor Viñals, Andrea Marongiu, Davide Bertozzi
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain. NOCS (2014)
Marta Ortín-Obón, Luca Ramini, Hervé Tatenguem Fankem, Víctor Viñals, Davide Bertozzi
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. ACM Great Lakes Symposium on VLSI (2014)
Marta Ortín-Obón, Luca Ramini, Víctor Viñals, Davide Bertozzi
Capturing the sensitivity of optical network quality metrics to its network interface parameters. Concurr. Comput. Pract. Exp. 26 (15) (2014)
Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems. J. Syst. Archit. 59 (9) (2013)
Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC (2013)
Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José María Llabería
Exploiting reuse locality on inclusive shared last-level caches. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería
The reuse cache: downsizing the shared last-level cache. MICRO (2013)
Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals
A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium (2012)
Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería
Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) (2011)
Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems. J. Syst. Archit. 57 (7) (2011)
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
Filtering directory lookups in CMPs. Microprocess. Microsystems 35 (8) (2011)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism 13 (2011)
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
Filtering Directory Lookups in CMPs. DSD (2010)
Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems. RTCSA (2010)
Benjamin Sahelices, Pablo Ibáñez, Víctor Viñals, José María Llabería
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par (2009)
Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals
Light NUCA: A proposal for bridging the inter-cache latency gap. DATE (2009)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Low-Cost Adaptive Data Prefetching. Euro-Par (2008)
Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD (2008)
Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, J. L. Villarroel, Víctor Viñals
Avoiding the WCET Overestimation on LRU Instruction Cache. RTCSA (2008)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
Microarchitectural Support for Speculative Register Renaming. IPDPS (2007)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35 (4) (2007)
Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström, José María Llabería
Characterization of Apache web server with Specweb2005. MEDEA@PACT (2007)
Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería
Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par (2006)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
Speculative early register release. Conf. Computing Frontiers (2006)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT (2006)
Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals
Software Demand, Hardware Supply. IEEE Micro 26 (4) (2006)
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3 (2/3) (2005)
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. 2 (3) (2005)
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
Store Buffer Design in First-Level Multibanked Data Caches. ISCA (2005)
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
Contents Management in First-Level Multibanked Data Caches. Euro-Par (2004)
Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53 (10) (2004)
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA (2003)
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par (2003)
María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT (2003)
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
Hardware Schemes for Early Register Release. ICPP (2002)
María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP (2001)
Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería
Modeling load address behaviour through recurrences. ISPASS (2000)
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000)
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO (1999)
Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán
Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing (1998)
Pablo Ibáñez, Víctor Viñals
Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO (1996)