Alejandro Valero

ORCID

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 15

Top Venues

IEEE Trans. Computers

Microprocess. Microsystems

CoRR

J. Syst. Archit.

Polytechnic University of Valencia, Spain (PHD)

Education History

Polytechnic University of Valencia, Spain

PHD

Publications

Yamilka Toca-Díaz, Reynier Hernández Palacios, Ruben Gran Tejero, Alejandro Valero
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage. Microprocess. Microsystems 106 (2024)
Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. DSD (2023)
Hugo Tárrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo
Fast-track cache: a huge racetrack memory L1 data cache. ICS (2022)
Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. 128 (2022)
Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS (2022)
Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. CoRR (2021)
Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez
A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. 156 (2021)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. IEEE Access 8 (2020)
Alejandro Valero, Francisco Candel, Darío Suárez Gracia, Salvador Petit, Julio Sahuquillo
An Aging-Aware GPU Register File Design Based on Data Redundancy. IEEE Trans. Computers 68 (1) (2019)
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA (2019)
Francisco Candel, Alejandro Valero, Salvador Petit, Julio Sahuquillo
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance. IEEE Trans. Computers 68 (10) (2019)
Francisco Candel, Salvador Petit, Alejandro Valero, Julio Sahuquillo
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache. Euro-Par (2018)
Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones
On Microarchitectural Mechanisms for Cache Wearout Reduction. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Francisco Candel, Alejandro Valero, Salvador Petit, Darío Suárez Gracia, Julio Sahuquillo
Exploiting Data Compression to Mitigate Aging in GPU Register Files. SBAC-PAD (2017)
Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones
Enhancing the L1 Data Cache Design to Mitigate HCI. IEEE Comput. Archit. Lett. 15 (2) (2016)
Alejandro Valero, Salvador Petit, Julio Sahuquillo, David R. Kaeli, José Duato
A reuse-based refresh policy for energy-aware eDRAM caches. Microprocess. Microsystems 39 (1) (2015)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
Design of Hybrid Second-Level Caches. IEEE Trans. Computers 64 (7) (2015)
Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo
Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. HPCC/CSS/ICESS (2014)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, José Duato
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. ICS (2013)
Vicente Lorente, Alejandro Valero, Ramon Canal
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. Euro-Par Workshops (2013)
Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE (2013)
Alejandro Valero, Salvador Petit, Julio Sahuquillo, Pedro López, José Duato
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. IEEE Trans. Computers 61 (9) (2012)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
Combining recency of information with selective random and a victim cache in last-level caches. ACM Trans. Archit. Code Optim. 9 (3) (2012)
Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
Analyzing the optimal ratio of SRAM banks in hybrid caches. ICCD (2012)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT (2011)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
MRU-Tour-based Replacement Algorithms for Last-Level Caches. SBAC-PAD (2011)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO (2009)

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Publication Activity (10 Years)

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Alejandro Valero