Vicente Lorente

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 1

Top Topics

Memory Bandwidth

Energy Consumption

Interconnection Networks

Top Venues

Euro-Par Workshops

Publications

Hugo Tárrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo
Fast-track cache: a huge racetrack memory L1 data cache. ICS (2022)
Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo
Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. HPCC/CSS/ICESS (2014)
Vicente Lorente, Alejandro Valero, Ramon Canal
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. Euro-Par Workshops (2013)
Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE (2013)
Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Vicente Lorente, Julio Sahuquillo
Effects of Process Variation on the Access Time in SRAM Cells. Euro-Par Workshops (2012)
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO (2009)