Sonia González-Navarro

Publication Activity (10 Years)

Years Active: 2007-2021
Publications (10 Years): 8

Top Topics

Comparative Study

Fractal Image Encoding

Sequence Alignment

Top Venues

IEEE Trans. Computers

IEEE ACM Trans. Comput. Biol. Bioinform.

Publications

Jose Manuel Herruzo, Ivan Fernandez, Sonia González-Navarro, Oscar G. Plata
Enabling fast and energy-efficient FM-index exact matching using processing-near-memory. J. Supercomput. 77 (9) (2021)
Sonia González-Navarro, Javier Hormigo
New Results on Non-Normalized Floating-Point Formats. IEEE Trans. Computers 69 (12) (2020)
Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez-Marín, Víctor Viñals Yúfera, Jesús Alastruey-Benedé, Oscar G. Plata
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. IEEE ACM Trans. Comput. Biol. Bioinform. 17 (4) (2020)
Julio Villalba, Javier Hormigo, Sonia González-Navarro
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs (6) (2019)
Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, Oscar G. Plata
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. DCC (2019)
Julio Villalba-Moreno, Javier Hormigo, Sonia González-Navarro
Unbiased Rounding for HUB Floating-Point Addition. IEEE Trans. Computers 67 (9) (2018)
Sonia González-Navarro, Javier Hormigo
Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. ARITH (2017)
Carlos Garcia-Vega, Sonia González-Navarro, Pedro Balboa-La Chica, Julio Villalba-Moreno
Decimal Multiformat Online Addition. IEEE Trans. Computers 65 (10) (2016)
Sonia González-Navarro, Charles Tsen, Michael J. Schulte
Binary Integer Decimal-Based Floating-Point Multiplication. IEEE Trans. Computers 62 (7) (2013)
Carlos Garcia-Vega, Sonia González-Navarro, Julio Villalba, Emilio L. Zapata
Decimal online multioperand addition. ACSCC (2012)
Carlos Garcia-Vega, Sonia González-Navarro, Julio Villalba-Moreno, Emilio L. Zapata
On-line Decimal Adder with RBCD Representation. ASAP (2012)
Sonia González-Navarro, Javier Hormigo, Michael J. Schulte
A study of decimal left shifters for binary numbers. Inf. Comput. 216 (2012)
Samuel Tsen, Sonia González-Navarro, Michael J. Schulte, Katherine Compton
Hardware Designs for Binary Integer Decimal-Based Rounding. IEEE Trans. Computers 60 (5) (2011)
Charles Tsen, Sonia González-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton
A Combined Decimal and Binary Floating-Point Multiplier. ASAP (2009)
Sonia González-Navarro, Juan López, Angeles G. Navarro, Emilio L. Zapata
Analytical Model of Patching and Load Sharing in a Distributed VoD System. PDPTA (2009)
Charles Tsen, Michael J. Schulte, Sonia González-Navarro
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. ASAP (2007)
Charles Tsen, Sonia González-Navarro, Michael J. Schulte
Hardware design of a Binary Integer Decimal-based floating-point adder. ICCD (2007)