Julio Villalba

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 6

Top Topics

Interval Arithmetic

Software Implementation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Computers

Publications

Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba
Floating Point HUB Adder for RISC-V Sargantana Processor. CoRR (2024)
Julio Villalba, Javier Hormigo
High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst. Signal Process. 41 (3) (2022)
Julio Villalba, Javier Hormigo, Sonia González-Navarro
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs (6) (2019)
Javier Hormigo, Julio Villalba
HUB Floating Point for Improving FPGA Implementations of DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Javier Hormigo, Julio Villalba
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Javier Hormigo, Julio Villalba
New Formats for Computing with Real-Numbers under Round-to-Nearest. IEEE Trans. Computers 65 (7) (2016)
Javier Hormigo, Julio Villalba
Simplified floating-point units for high dynamic range image and video systems. ISCE (2015)
Javier Hormigo, Julio Villalba
Optimizing DSP circuits by a new family of arithmetic operators. ACSSC (2014)
Julio Villalba, Javier Hormigo, Francisco Corbera, Mario A. González, Emilio L. Zapata
Efficient floating-point representation for balanced codes for FPGA devices. ICCD (2013)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Multioperand Redundant Adders on FPGAs. IEEE Trans. Computers 62 (10) (2013)
Carlos Garcia-Vega, Sonia González-Navarro, Julio Villalba, Emilio L. Zapata
Decimal online multioperand addition. ACSCC (2012)
Julio Villalba, Tomás Lang, Javier Hormigo
Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers 61 (6) (2012)
Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Enhanced Scaling-Free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos Diego Moreno-Moreno, Javier Hormigo, Julio Villalba
UCORE: Reconfigurable Platform for Educational Purposes. ReConFig (2010)
Álvaro Vázquez, Julio Villalba, Elisardo Antelo
Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic (2009)
Carlos Diego Moreno-Moreno, Francisco J. Quiles, Manuel Ortiz, María Brox, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS (2009)
Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata
Efficient Implementation of Carry-Save Adders in FPGAs. ASAP (2009)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Pipelined Architecture for Additive Range Reduction. J. Signal Process. Syst. 53 (1-2) (2008)
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
SIMD Enhancements for a Hough Transform Implementation. DSD (2008)
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
New SIMD instructions set for image processing applications enhancement. ICIP (2008)
Elisardo Antelo, Julio Villalba, Emilio L. Zapata
A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57 (3) (2008)
Julio Villalba, Javier Hormigo, Tomás Lang
Improving the Throughput of On-line Addition for Data Streams. ASAP (2007)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Pipelined Range Reduction for Floating Point Numbers. ASAP (2006)
Julio Villalba, Tomás Lang, Mario A. González
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. IEEE Trans. Computers 55 (3) (2006)
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata
SAD computation based on online arithmetic for motion estimation. Microprocess. Microsystems 30 (5) (2006)
Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL (2006)
Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata
On-line Multioperand Addition Based on On-line Full Adders. ASAP (2005)
Elisardo Antelo, Julio Villalba
Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic (2005)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
CORDIC Processor for Variable-Precision Interval Arithmetic. J. VLSI Signal Process. 37 (1) (2004)
Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Evaluation of Elementary Functions Using Multimedia Features. IPDPS (2004)
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL (2004)
Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata
Polynomial Evaluation on Multimedia Processors. ASAP (2002)
Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata
MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) (2000)
Javier Hormigo, Julio Villalba, Michael J. Schulte
A Hardware Algorithm for Variable-Precision Logarithm. ASAP (2000)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO (1999)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic (1999)
Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19 (2) (1998)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. SCAN (1998)
Julio Villalba, Tomás Lang, Emilio L. Zapata
Parallel Compensation of Scale Factor for the CORDIC Algorithm. J. VLSI Signal Process. 19 (3) (1998)
Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46 (8) (1997)
Julio Villalba, Tomás Lang
Low latency word serial CORDIC. ASAP (1997)
Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata
Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. 12 (3) (1996)
Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II (1996)
Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP (1996)
Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Digit On-line Large Radix CORDIC Rotator. ASAP (1995)
Nicolás Guil, Julio Villalba, Emilio L. Zapata
A fast Hough transform for segment detection. IEEE Trans. Image Process. 4 (11) (1995)
Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP (1995)
Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic (1995)