Elisardo Antelo

Publication Activity (10 Years)

Years Active: 1993-2019
Publications (10 Years): 6

Top Topics

Digital Computer

Special Section

Detection Scheme

Top Venues

IEEE Trans. Computers

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Álvaro Vázquez, Elisardo Antelo
New 3D Projection Transformation for Point Clouds. ARITH (2019)
Elisardo Antelo
ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]. CoRR (2019)
Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Álvaro Vázquez, Elisardo Antelo
A Number System Approach for Adder Topologies. ARITH (2017)
Álvaro Vázquez, Elisardo Antelo
A Sum Error Detection Scheme for Decimal Arithmetic. ARITH (2017)
Lois Orosa, Javier D. Bruguera, Elisardo Antelo
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. 59 (10) (2016)
Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera
Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers 63 (8) (2014)
Álvaro Vázquez, Julio Villalba-Moreno, Elisardo Antelo, Emilio L. Zapata
Redundant Floating-Point Decimal CORDIC Algorithm. IEEE Trans. Computers 61 (11) (2012)
Elisardo Antelo, David Hough, Paolo Ienne
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 61 (8) (2012)
Lois Orosa, Elisardo Antelo, Javier D. Bruguera
FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers. IEEE Trans. Computers 60 (2) (2011)
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
Improved Design of High-Performance Parallel Decimal Multipliers. IEEE Trans. Computers 59 (5) (2010)
Elisardo Antelo
A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network". IEEE Comput. Archit. Lett. 8 (1) (2009)
Álvaro Vázquez, Julio Villalba, Elisardo Antelo
Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic (2009)
Álvaro Vázquez, Elisardo Antelo
A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding. IEEE Symposium on Computer Arithmetic (2009)
Álvaro Vázquez, Elisardo Antelo
New insights on Ling adders. ASAP (2008)
Elisardo Antelo, Julio Villalba, Emilio L. Zapata
A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57 (3) (2008)
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
A radix-10 SRT divider based on alternative BCD codings. ICCD (2007)
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
A New Family of High.Performance Parallel Decimal Multipliers. IEEE Symposium on Computer Arithmetic (2007)
Tomás Lang, Elisardo Antelo
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. IEEE Trans. Computers 54 (3) (2005)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers 54 (7) (2005)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic (2005)
Elisardo Antelo, Julio Villalba
Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic (2005)
Álvaro Vázquez, Elisardo Antelo
Implementation of the Exponential Function in a Floating-Point Unit. J. VLSI Signal Process. 33 (1-2) (2003)
Tomás Lang, Elisardo Antelo
Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root. IEEE Trans. Computers 52 (9) (2003)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP (2002)
Tomás Lang, Elisardo Antelo
Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. IEEE Symposium on Computer Arithmetic (2001)
Tomás Lang, Elisardo Antelo
CORDIC-Based Computation of ArcCos. J. VLSI Signal Process. 25 (1) (2000)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49 (7) (2000)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. 25 (2) (2000)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic (1999)
Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19 (2) (1998)
Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. 6 (1) (1998)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47 (2) (1998)
Tomás Lang, Elisardo Antelo
CORDIC Vectoring with Arbitrary Target Value. IEEE Trans. Computers 47 (7) (1998)
Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46 (11) (1997)
Tomás Lang, Elisardo Antelo
CORDIC Vectoring with Arbitrary Target Value. IEEE Symposium on Computer Arithmetic (1997)
Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46 (8) (1997)
Tomás Lang, Elisardo Antelo
CORDIC-based computation of arccos and arcsin. ASAP (1997)
Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata
Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45 (9) (1996)
Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II (1996)
Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP (1996)
Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Digit On-line Large Radix CORDIC Rotator. ASAP (1995)
Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP (1995)
Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic (1995)
Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata
Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. 19 (7) (1993)