Javier D. Bruguera

ORCID

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 7

Top Venues

IEEE Trans. Computers

ARITH

Comput. J.

Sci. Comput. Program.

Publications

Javier D. Bruguera
Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units. IEEE Trans. Computers 72 (10) (2023)
Javier D. Bruguera
Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit. ARITH (2022)
Javier D. Bruguera
Low Latency Floating-Point Division and Square Root Unit. IEEE Trans. Computers 69 (2) (2020)
Javier D. Bruguera, Florent de Dinechin
Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 68 (7) (2019)
Javier D. Bruguera
Radix-64 Floating-Point Divider. ARITH (2018)
E. G. Paredes, Margarita Amor, Montserrat Bóo, Javier D. Bruguera, Jürgen Döllner
Hybrid terrain rendering based on the external edge primitive. Int. J. Geogr. Inf. Sci. 30 (6) (2016)
Lois Orosa, Javier D. Bruguera, Elisardo Antelo
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. 59 (10) (2016)
Daniel Piso Fernandez, Javier D. Bruguera
Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms. Comput. J. 57 (2) (2014)
Javier D. Bruguera
Optimizing the representation of intervals. Sci. Comput. Program. 90 (2014)
Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera
Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers 63 (8) (2014)
Álvaro Vázquez, Javier D. Bruguera
Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction. IEEE Trans. Computers 62 (9) (2013)
Roberto R. Osorio, Javier D. Bruguera
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. 72 (2) (2013)
Marc Daumas, Javier D. Bruguera
8th Conference on Real Numbers and Computers. Inf. Comput. 216 (2012)
E. G. Paredes, Montserrat Bóo, Margarita Amor, Jürgen Döllner, Javier D. Bruguera
GPU-based Visualization of Hybrid Terrain Models. GRAPP/IVAPP (2012)
E. G. Paredes, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Jürgen Döllner
Extended hybrid meshing algorithm for multiresolution terrain models. Int. J. Geogr. Inf. Sci. 26 (5) (2012)
Lois Orosa, Elisardo Antelo, Javier D. Bruguera
FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Javier D. Bruguera, Marius Cornea, Debjit Das Sarma
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 60 (2) (2011)
Álvaro Vázquez, Javier D. Bruguera
Composite Iterative Algorithm and Architecture for q-th Root Calculation. IEEE Symposium on Computer Arithmetic (2011)
Daniel Piso Fernandez, Javier D. Bruguera
Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. IEEE Trans. Computers 60 (11) (2011)
Daniel Piso Fernandez, Javier D. Bruguera
Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. DSD (2009)
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera
High Performance Image Processing on a Massively Parallel Processor Array. DSD (2009)
Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi
A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Trans. Computers 57 (4) (2008)
Daniel Piso Fernandez, Javier D. Bruguera
A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. DSD (2008)
Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson
Topic 10: Parallel Numerical Algorithms. Euro-Par (2008)
Roberto R. Osorio, Javier D. Bruguera
An FPGA architecture for CABAC decoding in manycore systems. ASAP (2008)
Daniel Piso Fernandez, Javier D. Bruguera
Forcing one-sided results in Goldschmidt algorithm. ACSCC (2008)
Roberto R. Osorio, Javier D. Bruguera
Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP (2007)
F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Hardware support for adaptive tessellation of Bézier surfaces based on local tests. J. Syst. Archit. 53 (4) (2007)
Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro
A Digit-by-Digit Algorithm for mth Root Extraction. IEEE Trans. Computers 56 (12) (2007)
Roberto R. Osorio, Javier D. Bruguera
High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. 16 (11) (2006)
Roberto R. Osorio, Javier D. Bruguera
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD (2006)
Javier D. Bruguera, Roberto R. Osorio
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD (2006)
Viay Holimath, Javier D. Bruguera
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. DSD (2006)
Roberto R. Osorio, Javier D. Bruguera
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD (2005)
F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. WSCG (Short Papers) (2005)
José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera
High-Speed Function Approximation Using a Minimax Quadratic Interpolator. IEEE Trans. Computers 54 (3) (2005)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. J. VLSI Signal Process. 40 (1) (2005)
Javier D. Bruguera, Tomás Lang
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic (2005)
Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Algorithms and Hardware for Data Compression in Point Rendering Applications. WSCG (Short Papers) (2004)
Roberto R. Osorio, Javier D. Bruguera
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD (2004)
Tomás Lang, Javier D. Bruguera
Floating-Point Multiply-Add-Fused with Reduced Latency. IEEE Trans. Computers 53 (8) (2004)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53 (9) (2004)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic (2003)
María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
High performance air pollution modeling for a power plant environment. Parallel Comput. 29 (11-12) (2003)
Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez
Research Article: A GIS-embedded system to support land consolidation plans in Galicia. Int. J. Geogr. Inf. Sci. 17 (4) (2003)
Javier D. Bruguera, Tomás Lang
Multilevel Reverse-Carry Addition: Single and Dual Adders. J. VLSI Signal Process. 33 (1-2) (2003)
F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Adaptive Tessellation of NURBS Surfaces. WSCG (2003)
Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. J. Syst. Archit. 49 (12-15) (2003)
José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac
On-line high-radix exponential with selection by rounding. ISCAS (4) (2003)
Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Hardware Implementation of the Subdivision Loop Algorithm. EUROMICRO (2002)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD (2002)
Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. 3DPVT (2002)
Tomás Lang, Javier D. Bruguera
Floating-Point Fused Multiply-Add with Reduced Latency. ICCD (2002)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding. ASAP (2002)
José-Alejandro Piñeiro, Javier D. Bruguera
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Trans. Computers 51 (12) (2002)
Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. DSD (2002)
José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. DSD (2001)
Javier D. Bruguera, Tomás Lang
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. IEEE Symposium on Computer Arithmetic (2001)
Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
Implementation of a NURBS to Bézier Conversor with Constant Latency. FPL (2001)
José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. IEEE Symposium on Computer Arithmetic (2001)
Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González
COPA: a GIS-based Tool for Land Consolidation Projects. ACM-GIS (2001)
José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera
The STEM-II Air Quality Model on a Distributed Memory System. ICPP Workshops (2001)
Javier D. Bruguera, Tomás Lang
Multilevel reverse most-significant carry computation. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
Parallelization of the STEM-II Air Quality Model. HPCN Europe (2001)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49 (7) (2000)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. 25 (2) (2000)
Carlos E. Cabrera Reyes, Javier D. Bruguera
VLSI systolic array architecture for the lattice structure of the discrete wavelet transform. ISCAS (2000)
Roberto R. Osorio, Javier D. Bruguera
Architectures for arithmetic coding in image compression. EUSIPCO (2000)
Javier D. Bruguera, Tomás Lang
Multilevel Reverse-Carry Adder. ICCD (2000)
Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. EUROMICRO (2000)
Roberto R. Osorio, Javier D. Bruguera
New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS (1999)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic (1999)
Tomás Lang, Javier D. Bruguera
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ICCD (1999)
Javier D. Bruguera, Tomás Lang
Leading-One Prediction with Concurrent Position Correction. IEEE Trans. Computers 48 (10) (1999)
Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19 (2) (1998)
Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. 6 (1) (1998)
Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO (1998)
Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47 (2) (1998)
Javier D. Bruguera, Tomás Lang
Leading-one prediction scheme for latency improvement in single datapath floating-point adders. ICCD (1998)
Carlos Cabrera, Montserrat Bóo, Javier D. Bruguera
VLSI implementation of an area-efficient architecture for the Viterbi algorithm. ICASSP (1997)
Roberto R. Osorio, Javier D. Bruguera
New arithmetic coder/decoder architectures based on pipelining. ASAP (1997)
Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera
A VLSI implementation of an arithmetic coder for image compression. EUROMICRO (1997)
Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46 (11) (1997)
Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata
High-performance VLSI architecture for the Viterbi algorithm. IEEE Trans. Commun. 45 (2) (1997)
Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. J. VLSI Signal Process. 17 (1) (1997)
Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46 (8) (1997)
Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata
Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45 (9) (1996)
Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata
Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. 12 (3) (1996)
Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
High performance VLSI architecture for the trellis coded quantization. ICIP (2) (1996)
Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II (1996)
Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ASAP (1996)
Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP (1996)
Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Digit On-line Large Radix CORDIC Rotator. ASAP (1995)
Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
A Parallel Architecture for the Self-Sorting FFT Algorithm. J. Parallel Distributed Comput. 31 (1) (1995)
Javier D. Bruguera, Tomás Lang
2-D DCT using on-line arithmetic. ICASSP (1995)
Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP (1995)
Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic (1995)
Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata
Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Trans. Parallel Distributed Syst. 5 (10) (1994)
Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata
Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. 19 (7) (1993)
Emilio L. Zapata, Ignacio Benavides, Francisco F. Rivera, Javier D. Bruguera, Tomás F. Pena, José María Carazo
Image reconstruction on hypercube computers: Application to electron microscopy. Signal Process. 27 (1) (1992)

Javier D. Bruguera.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Javier D. Bruguera