High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard.
Roberto R. OsorioJavier D. BrugueraPublished in: J. Signal Process. Syst. (2013)
Keyphrases
- high speed
- real time
- low power
- hardware architecture
- fpga implementation
- hardware architectures
- hardware design
- management system
- dedicated hardware
- data acquisition
- frame rate
- multiresolution
- high speed networks
- low cost
- motion estimation
- decoding algorithm
- master slave
- hardware implementation
- decoding process
- video decoder
- pipelined architecture