Roberto R. Osorio

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 8

Top Topics

High Compression

Fpga Implementation

Motion Estimation Algorithm

Top Venues

New Gener. Comput.

Publications

Roberto R. Osorio
Floating Point Calculation of the Cube Function on FPGAs. IEEE Trans. Parallel Distributed Syst. 34 (1) (2023)
Manuel de Castro, Roberto R. Osorio, David López Vilariño, Arturo González-Escribano, Diego R. Llanos
Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL. J. Supercomput. 79 (9) (2023)
Patricia González, Roberto R. Osorio, Xoán C. Pardo, Julio R. Banga, Ramón Doallo
An efficient ant colony optimization framework for HPC environments. Appl. Soft Comput. 114 (2022)
Roberto R. Osorio, Gabriel Rodríguez
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors. IEEE Access 7 (2019)
Javier Cereijo García, Roberto R. Osorio
A Microprogrammed Approach for Implementing Statecharts. DSD (2019)
Javier Cereijo García, Roberto R. Osorio
Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities. DCIS (2019)
Roberto R. Osorio, Patricia González
A fast algorithm for constructing nearly optimal prefix codes. Softw. Pract. Exp. 46 (10) (2016)
Roberto R. Osorio
Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model. ASAP (2016)
Iván Cores, Gabriel Rodríguez, María J. Martín, Patricia González, Roberto R. Osorio
Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes. New Gener. Comput. 31 (3) (2013)
Roberto R. Osorio, Javier D. Bruguera
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. 72 (2) (2013)
Angela Souto Vieites, Roberto R. Osorio
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. DSD (2013)
Roberto R. Osorio, Patricia González
Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting. DCC (2012)
Alejandro Nieto, Víctor M. Brea, David López Vilariño, Roberto R. Osorio
Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP J. Image Video Process. 2011 (2011)
Cesar Diaz-Resco, Alejandro Nieto, Roberto R. Osorio, Víctor M. Brea, David López Vilariño
A digital cellular-based system for retinal vessel-tree extraction. ECCTD (2009)
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera
High Performance Image Processing on a Massively Parallel Processor Array. DSD (2009)
Roberto R. Osorio, Javier D. Bruguera
An FPGA architecture for CABAC decoding in manycore systems. ASAP (2008)
Roberto R. Osorio, Javier D. Bruguera
Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP (2007)
Roberto R. Osorio, Javier D. Bruguera
High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. 16 (11) (2006)
Roberto R. Osorio, Javier D. Bruguera
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD (2006)
Javier D. Bruguera, Roberto R. Osorio
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD (2006)
Roberto R. Osorio, Javier D. Bruguera
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD (2005)
Roberto R. Osorio, Javier D. Bruguera
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD (2004)
Gauthier Lafruit, Eric Delfosse, Roberto R. Osorio, Wolfgang van Raemdonck, Vissarion Ferentinos
View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding. IEEE Trans. Circuits Syst. Video Technol. 14 (7) (2004)
Roberto R. Osorio, Bart Vanhoof
High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. J. VLSI Signal Process. 33 (3) (2003)
Roberto R. Osorio, Sylvain Devillers, Eric Delfosse, Myriam Amielh, Gauthier Lafruit
Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streaming. ICIP (3) (2002)
Roberto R. Osorio, Javier D. Bruguera
Architectures for arithmetic coding in image compression. EUSIPCO (2000)
Roberto R. Osorio, Javier D. Bruguera
New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS (1999)
Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO (1998)
Roberto R. Osorio, Javier D. Bruguera
New arithmetic coder/decoder architectures based on pipelining. ASAP (1997)
Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera
A VLSI implementation of an arithmetic coder for image compression. EUROMICRO (1997)
Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
Digit On-line Large Radix CORDIC Rotator. ASAP (1995)