A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems.
Roberto R. OsorioJavier D. BrugueraPublished in: DSD (2006)
Keyphrases
- embedded systems
- video encoding
- motion estimation
- computing power
- low complexity
- hardware software
- computational power
- low cost
- flash memory
- video coding
- resource constrained
- protocol stack
- image sequences
- video sequences
- video encoder
- motion vectors
- motion compensation
- video compression
- block matching
- optical flow
- inter frame
- motion compensated
- computational complexity
- compression ratio
- spatial domain
- rate distortion
- random access
- reference frame
- low bit rate
- compression efficiency
- image compression
- software systems
- motion field
- real time
- computer vision
- data compression
- compression algorithm
- bit allocation
- multithreading
- digital video
- distributed video coding
- reduce the computational complexity
- coding efficiency
- parallel processing
- main memory