Milos D. Ercegovac

ORCID

Publication Activity (10 Years)

Years Active: 1972-2024
Publications (10 Years): 17

Top Venues

ACSSC

CoRR

ACSCC

IEEE Trans. Computers

Publications

David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek
Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers 73 (1) (2024)
Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
Multiplier Optimization via E-Graph Rewriting. CoRR (2023)
Saeid Gorgin, Mohammad H. Golamrezaei, Jeong-A Lee, Milos D. Ercegovac
An Efficient Dot-Product Unit Based on Online Arithmetic for Variable Precision Applications. ACSSC (2023)
Muhammad Usman, Milos D. Ercegovac, Jeong-A Lee
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. CoRR (2023)
Tooba Arifeen, Saeid Gorgin, MohammadHosein Gholamrezaei, Abdus Sami Hassan, Milos D. Ercegovac, Jeong-A Lee
Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product. J. Signal Process. Syst. 95 (7) (2023)
Saeid Gorgin, Mohammadreza Najafi, Mohammad H. Golamrezaei, Jeong-A Lee, Milos D. Ercegovac
MSDF-SVM: Advantage of Most Significant Digit First Arithmetic for SVM Realization. ACSSC (2023)
Muhammad Usman, Milos D. Ercegovac, Jeong-A Lee
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. J. Signal Process. Syst. 95 (7) (2023)
Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
Multiplier Optimization via E-Graph Rewriting. ACSSC (2023)
Muhammad Usman, Jeong A. Lee, Milos D. Ercegovac
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. CoRR (2022)
Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee, Milos D. Ercegovac
Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products. ACSCC (2021)
Muhammad Usman, Jeong A. Lee, Milos D. Ercegovac
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. ACSCC (2021)
James E. Stine, Milos D. Ercegovac, Jean-Michel Muller
An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. ACSSC (2020)
Milos D. Ercegovac
On Reducing Module Activities in Online Arithmetic Operations. ACSSC (2020)
Milos D. Ercegovac, James E. Stine
Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. ACSSC (2019)
Milos D. Ercegovac
On left-to-right arithmetic. ACSSC (2017)
Wen Yan, Milos D. Ercegovac, He Chen
An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Wen Yan, Milos D. Ercegovac
Radix-4 energy efficient carry-free truncated multiplier. ACSSC (2016)
Ching-En Lee, Milos D. Ercegovac
An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration. ACSSC (2015)
Dong Wang, Jean-Michel Muller, Nicolas Brisebarre, Milos D. Ercegovac
(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function. IEEE Trans. Circuits Syst. II Express Briefs (9) (2014)
Milos D. Ercegovac, Lu Meng
Low-power radix-4 quotient generator. ACSSC (2014)
Dong Wang, Milos D. Ercegovac, Yang Xiao
Complex Function Approximation Using Two-Dimensional Interpolation. IEEE Trans. Computers 63 (12) (2014)
Hojat Parta, Milos D. Ercegovac, Sudhakar Pamarti
RF digital predistorter implementation using polynomial optimization. MWSCAS (2014)
Milos D. Ercegovac
On approximate arithmetic. ACSSC (2013)
Seok Won Heo, Suk Joong Huh, Milos D. Ercegovac
Power optimization in a parallel multiplier using voltage islands. ISCAS (2013)
Jason Cong, Milos D. Ercegovac, Muhuan Huang, Sen Li, Bingjun Xiao
Energy-efficient computing using adaptive table lookup based on nonvolatile memories. ISLPED (2013)
Seok Won Heo, Suk Joong Huh, Milos D. Ercegovac
Power optimization of sum-of-products design for signal processing applications. ASAP (2013)
Milos D. Ercegovac, Robert McIlhenny
Shared implementation of radix-10 and radix-16 square root algorithm with limited precision primitives. ACSCC (2012)
Dong Wang, Milos D. Ercegovac
A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling. IEEE Trans. Computers 61 (9) (2012)
Milos D. Ercegovac
Session TP8a3: Design methodology and computer arithmetic. ACSCC (2012)
Pouya Dormiani, Milos D. Ercegovac
Linearization using efficient complex polynomial evaluations. ACSCC (2012)
Nicolas Brisebarre, Milos D. Ercegovac, Jean-Michel Muller
(M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation. ASAP (2012)
Shawn Singh, Seung hyun Pan, Milos D. Ercegovac
Accelerating the photon mapping algorithm and its hardware implementation. ASAP (2011)
Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac
Trading Accuracy for Power with an Underdesigned Multiplier Architecture. VLSI Design (2011)
Milos D. Ercegovac, Robert McIlhenny
Shared implementation of radix-10 and radix-16 division algorithm with limited precision primitives. ACSCC (2011)
Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac
Trading Accuracy for Power in a Multiplier Architecture. J. Low Power Electron. 7 (4) (2011)
Nicolas Brisebarre, Nicolas Louvet, Érik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, Milos D. Ercegovac
Implementing decimal floating-point arithmetic through binary: Some suggestions. ASAP (2010)
Dong Wang, Milos D. Ercegovac, Nanning Zheng
Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit. IEEE Trans. Circuits Syst. II Express Briefs (8) (2010)
Jean-Claude Bajard, Sylvain Duquesne, Milos D. Ercegovac
and RNS representation. IACR Cryptol. ePrint Arch. 2010 (2010)
Milos D. Ercegovac, Jean-Michel Muller
An Efficient Method for Evaluating Complex Polynomials. J. Signal Process. Syst. 58 (1) (2010)
Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. J. Circuits Syst. Comput. 18 (4) (2009)
Dong Wang, Milos D. Ercegovac, Nanning Zheng
A radix-8 complex divider for FPGA implementation. FPL (2009)
Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller
Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. ASAP (2009)
Milos D. Ercegovac, Robert McIlhenny
Design and FPGA implementation of radix-10 algorithm for division with limited precision primitives. ACSCC (2008)
Nicolas Brisebarre, Sylvain Chevillard, Milos D. Ercegovac, Jean-Michel Muller, Serge Torres
An efficient method for evaluating polynomial and rational function approximations. ASAP (2008)
Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. MICRO (2007)
Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac
A Design Method for Heterogeneous Adders. ICESS (2007)
Milos D. Ercegovac, Jean-Michel Muller
A Hardware-Oriented Method for Evaluating Complex Polynomials. ASAP (2007)
Milos D. Ercegovac, Jean-Michel Muller
Complex Square Root with Operand Prescaling. J. VLSI Signal Process. 49 (1) (2007)
Pavan Adharapurapu, Milos D. Ercegovac
A Linear-System Operator Based Scheme for Evaluation of Multinomials. IEEE Symposium on Computer Arithmetic (2005)
Robert McIlhenny, Milos D. Ercegovac
RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions. FCCM (2005)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. J. VLSI Signal Process. 40 (1) (2005)
Zhijun Huang, Milos D. Ercegovac
High-Performance Low-Power Left-to-Right Array Multiplier Design. IEEE Trans. Computers 54 (3) (2005)
Milos D. Ercegovac, Jean-Michel Muller
Variable Radix Real and Complex Digit-Recurrence Division. ASAP (2005)
Milos D. Ercegovac, Jean-Michel Muller
Complex Square Root with Operand Prescaling. ASAP (2004)
David A. Rennels, Milos D. Ercegovac
From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis. IFIP Congress Topical Sessions (2004)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53 (9) (2004)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic (2003)
Zhijun Huang, Milos D. Ercegovac
High-Performance Left-to-Right Array Multiplier Design. IEEE Symposium on Computer Arithmetic (2003)
Milos D. Ercegovac, Tomás Lang, Y. Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig
Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm". IEEE J. Solid State Circuits 38 (1) (2003)
Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
Performance-driven mapping for CPLD architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (10) (2003)
José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac
On-line high-radix exponential with selection by rounding. ISCAS (4) (2003)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD (2002)
Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac
High-Level Synthesis with SIMD Units. VLSI Design (2002)
José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding. ASAP (2002)
Zhijun Huang, Milos D. Ercegovac
Two-dimensional signal gating for low-power array multiplier design. ISCAS (1) (2002)
Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor
A FPGA-based Library for On-Line Signal Processing. J. VLSI Signal Process. 28 (1-2) (2001)
Zhijun Huang, Milos D. Ercegovac
FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization. FCCM (2001)
Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
Performance-driven mapping for CPLD architectures. FPGA (2001)
Aaron Schneider, Robert McIlhenny, Milos D. Ercegovac
BigSky-An On-Line Arithmetic Design Tool for FPGAs. FCCM (2000)
Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. IEEE Trans. Computers 49 (7) (2000)
Jeffrey M. Fischer, Milos D. Ercegovac
A Component Framework for Communication in Distributed Applications. IPDPS (2000)
Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. IEEE Trans. Computers 49 (7) (2000)
Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor
FPGA-Based Structures for On-Line FFT and DCT. FCCM (1999)
Milos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak
Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. DAC (1999)
Alexandre F. Tenca, Milos D. Ercegovac
On the Design of High-Radix On-Line Division for Long Precision. IEEE Symposium on Computer Arithmetic (1999)
Alexandre F. Tenca, Milos D. Ercegovac
A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. FCCM (1998)
Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac
Long and Fast Up/Down Counters. IEEE Trans. Computers 47 (7) (1998)
Milos D. Ercegovac, Darko Kirovski, George Mustafa, Miodrag Potkonjak
Behavioral synthesis optimization using multiple precision arithmetic. ICASSP (1998)
Alexandre F. Tenca, Milos D. Ercegovac
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. FPGA (1997)
Milos D. Ercegovac, Tomás Lang
On recoding in arithmetic algorithms. J. VLSI Signal Process. 14 (3) (1996)
Raffi Dionysian, Milos D. Ercegovac
Vector quantization with compressed codebooks. Signal Process. Image Commun. 9 (1) (1996)
Raffi Dionysian, Milos D. Ercegovac
Vector quantization with variable-precision classification. IEEE Trans. Image Process. 5 (11) (1996)
Marianne E. Louie, Milos D. Ercegovac
A variable-precision square root implementation for field programmable gate arrays. J. Supercomput. 9 (3) (1995)
Milos D. Ercegovac, Tomás Lang
Sign detection and comparison networks with a small number of transitions. IEEE Symposium on Computer Arithmetic (1995)
Milos D. Ercegovac, Tomás Lang, Paolo Montuschi
Very-High Radix Division with Prescaling and Selection by Rounding. IEEE Trans. Computers 43 (8) (1994)
Marianne E. Louie, Milos D. Ercegovac
Implementing division with field programmable gate arrays. J. VLSI Signal Process. 7 (3) (1994)
John S. Fernando, Milos D. Ercegovac
Conventional and on-line arithmetic designs for high-speed recursive digital filters. J. VLSI Signal Process. 7 (3) (1994)
Marianne E. Louie, Milos D. Ercegovac
On digit-recurrence division implementations for field programmable gate arrays. IEEE Symposium on Computer Arithmetic (1993)
James J. Liu, Milos D. Ercegovac
Symbolic Synthesis of Parallel Processing Systems. IPPS (1993)
Milos D. Ercegovac, Tomás Lang, Paolo Montuschi
Very high radix division with selection by rounding and prescaling. IEEE Symposium on Computer Arithmetic (1993)
James J. Liu, Milos D. Ercegovac
ALIAS Environment: A Design Tool for Application Specific Arrays. SPDP (1993)
Milos D. Ercegovac, Tomás Lang
Multiplication/ division/ square root module for massively parallel computers. Integr. 16 (3) (1993)
Leon Alkalaj, Tomás Lang, Milos D. Ercegovac
Architectural Support for Goal Management in Flat Concurrent Prolog. Computer 25 (8) (1992)
Milos D. Ercegovac, Tomás Lang
On-the-Fly Rounding. IEEE Trans. Computers 41 (12) (1992)
Dinh Lê, Milos D. Ercegovac, Tomás Lang, Jaime H. Moreno
MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs. ASAP (1992)
Raffi Dionysian, Milos D. Ercegovac
Variable Precision Representation for Efficient VQ Codebook Storage. Data Compression Conference (1992)
Alex Kapelnikov, Richard R. Muntz, Milos D. Ercegovac
A methodology for performance analysis of parallel computations with looping constructs. J. Parallel Distributed Comput. 14 (2) (1992)
Paul K.-G. Tu, Milos D. Ercegovac
Gate array implementation of on-line algorithms for floating-point operations. J. VLSI Signal Process. 3 (4) (1991)
Paul K.-G. Tu, Milos D. Ercegovac
Application of on-line arithmetic algorithms to the SVD computation: preliminary results. IEEE Symposium on Computer Arithmetic (1991)
Milos D. Ercegovac, Tomás Lang
Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations. J. Parallel Distributed Comput. 11 (3) (1991)

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Publication Activity (10 Years)

Top Topics

Top Venues

Milos D. Ercegovac