James E. Stine

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 35

Top Topics

Hardware Implementation

Hardware Architecture

Top Venues

Publications

David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek
Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers 73 (1) (2024)
Ryan Ridley, James E. Stine, George Suárez
Methodologies for Implementation of Standard-Cell Libraries for Radiation Hardened Environments. LASCAS (2024)
Alexander Underwood, James E. Stine
Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures. ACSSC (2023)
Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR (2023)
Ryan Swann, James E. Stine
Evaluation of a Modular Approach to AES Hardware Architecture and Optimization. J. Signal Process. Syst. 95 (7) (2023)
Ryan Swann, James E. Stine
Parallelization of the Shift and Add Reducer. ACSSC (2023)
Brett Mathis, James E. Stine
Implementation of High Performance IEEE 754-Posit Conversion Hardware. ISCAS (2022)
Teodor-Dumitru Ene, James E. Stine
Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees. ARITH (2022)
Ryan Swann, James E. Stine
A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware. ACSCC (2021)
Teodor-Dumitru Ene, James E. Stine
A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. ICCD (2021)
James E. Stine, Kevin Hill
An Efficient Implementation of Radix-4 Integer Division Using Scaling. MWSCAS (2020)
S. Ross Thompson, James E. Stine
A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication. MWSCAS (2020)
James E. Stine, Milos D. Ercegovac, Jean-Michel Muller
An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. ACSSC (2020)
Ryan Swann, James E. Stine
An Improved Hardware Architecture for modulo without Multiplication. MWSCAS (2020)
S. Ross Thompson, James E. Stine
A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier. ICCD (2020)
Brett Mathis, James E. Stine
A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. ISVLSI (2019)
Alexander Underwood, James E. Stine
An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education. WCAE@ISCA (2019)
Brett Mathis, James E. Stine
A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. ASAP (2019)
Kyle Price, James E. Stine
Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures. MWSCAS (2019)
Milos D. Ercegovac, James E. Stine
Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. ACSSC (2019)
Bin Wu, James E. Stine, Matthew R. Guthaus
Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS (2019)
Matthew Gaalswyk, James E. Stine
A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition. ISVLSI (2019)
Tuan D. Nguyen, Son Bui, James E. Stine
Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication. ASAP (2018)
John D. Tobola, James E. Stine
Low-Area Memoryless optimized Soft-Decision Viterbi Decoder with Dedicated Paralell Squaring Architecture. ACSSC (2018)
Samira Ataei, James E. Stine
A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. IEEE Embed. Syst. Lett. 10 (1) (2018)
Samira Ataei, James E. Stine
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. SoCC (2018)
Samira Ataei, Matthew Gaalswyk, James E. Stine
A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. MWSCAS (2017)
Donald Kline Jr., Nikolas Parshook, Alex Johnson, James E. Stine, William Stanchina, Erik Brunvand, Alex K. Jones
Sustainable IC design and fabrication. IGSC (2017)
Tuan D. Nguyen, James E. Stine
A combined IEEE half and single precision floating point multipliers for deep learning. ACSSC (2017)
Son Bui, James E. Stine
Constant-based truncated cubing architectures. MWSCAS (2017)
Rabin Thapa, Samira Ataei, James E. Stine
WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. MSE (2017)
Samira Ataei, James E. Stine
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. ACM Great Lakes Symposium on VLSI (2017)
Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar
OpenRAM: an open-source memory compiler. ICCAD (2016)
James E. Stine, Masoud Sadeghian
Optimized multipartite table methods for elementary function computation. ACSSC (2016)
Samira Ataei, James E. Stine, Matthew R. Guthaus
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD (2016)
S. Ross Thompson, James E. Stine
An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers. ASAP (2015)
Sampoorna Mallipeddi, James E. Stine
Revisiting redundant Booth with bias multipliers. MWSCAS (2015)
Samira Ataei, James E. Stine
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. ACM Great Lakes Symposium on VLSI (2015)
Samira Ataei, James E. Stine
A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. IGSC (2015)
Mehedi Sarwar, James E. Stine
Enhancing the Unified Logical Effort algorithm for branching and load distribution. ISCAS (2014)
Son Bui, James E. Stine
Additional optimizations for parallel squarer units. ISCAS (2014)
Son Bui, James E. Stine, Masoud Sadeghian
Experiments with High Speed Parallel Cubing Units. ISVLSI (2014)
Masoud Sadeghian, James E. Stine, E. George Walters III
Optimized cubic chebyshev interpolator for elementary function hardware implementations. ISCAS (2014)
Masoud Sadeghian, James E. Stine
Optimized low-power elementary function approximation for Chebyshev series approximations. ACSCC (2012)
Masoud Sadeghian, James E. Stine
Elementary function approximation using optimized most significant bits of Chebyshev coefficients and truncated multipliers. MWSCAS (2012)
James E. Stine
Session TA6b: Low power II (invited). ACSCC (2012)
James E. Stine, Amey Phadke, Surpriya Tike
A recursive-divide architecture for multiplication and division. ISCAS (2011)
Jun Chen, James E. Stine
Parallel Prefix Ling Structures for Modulo 2^n-1 Addition. ASAP (2009)
James E. Stine, Jun Chen, Ivan D. Castellanos, Gopal Sundararajan, Mohammad A. Qayum, Praveen Kumar, Justin Remington, Sohum Sohoni
FreePDK v2.0: Transitioning VLSI education towards nanometer variation-aware designs. MSE (2009)
Harsha Choday, James E. Stine
Single-ended half-swing low-power SRAM design. ACSCC (2008)
James E. Stine
Session WA5b: Low power methods. ACSCC (2008)
Ivan D. Castellanos, James E. Stine
Compressor trees for decimal partial product reduction. ACM Great Lakes Symposium on VLSI (2008)
James E. Stine, Ivan D. Castellanos, Michael H. Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, Ravi Jenkal
FreePDK: An Open-Source Variation-Aware Design Kit. MSE (2007)
James E. Stine, Jeff M. Blank
Partial Product Reduction for Parallel Cubing. ISVLSI (2007)
Johannes Grad, James E. Stine
Low power binary addition using carry increment adders. ISCAS (2006)
James E. Stine, Nitin Naresh
Compressed symmetric tables for accurate function approximation of reciprocals. ISCAS (2006)
Johannes Grad, James E. Stine
Dual-Mode High-Speed Low-Energy Binary Addition. ISVLSI (2006)
Ivan D. Castellanos, James E. Stine
A 64-bit Decimal Floating-Point Comparator. ASAP (2006)
Johannes Grad, James E. Stine
New algorithms for carry propagation. ACM Great Lakes Symposium on VLSI (2005)
James E. Stine, Christopher R. Babb, Vibhuti B. Dave
Constant addition utilizing flagged prefix structures. ISCAS (1) (2005)
James E. Stine, Michael J. Schulte
A combined two's complement and floating-point comparator. ISCAS (1) (2005)
James E. Stine, Johannes Grad, Ivan D. Castellanos, Jeff M. Blank, Vibhuti B. Dave, Mallika Prakash, Nick Iliev, Nathan Jachimiec
A Framework for High-Level Synthesis of System-on-Chip Designs. MSE (2005)
Johannes Grad, James E. Stine, David D. Neiman
Real World SOC Experience for the Classroom. MSE (2005)
Ahmet Akkas, Michael J. Schulte, James E. Stine
Intrinsic Compiler Support for Interval Arithmetic. Numer. Algorithms 37 (1-4) (2004)
Alok A. Katkar, James E. Stine
Modified booth truncated multipliers. ACM Great Lakes Symposium on VLSI (2004)
Nick Iliev, James E. Stine, Nathan Jachimiec
Parallel Programmable Finite Field GF(2m) Multipliers. ISVLSI (2004)
James E. Stine, Oliver M. Duverne
Variations on Truncated Multiplication. DSD (2003)
Bhushan A. Shinkre, James E. Stine
A pipelined clock-delayed domino carry-lookahead adder. ACM Great Lakes Symposium on VLSI (2003)
Johannes Grad, James E. Stine
A Standard Cell Library for Student Projects. MSE (2003)
Kent E. Wires, Michael J. Schulte, James E. Stine
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. ICCD (2001)
Michael J. Schulte, James E. Stine
Approximating Elementary Functions with Symmetric Bipartite Tables. IEEE Trans. Computers 48 (8) (1999)
James E. Stine, Michael J. Schulte
The Symmetric Table Addition Method for Accurate Function Approximation. J. VLSI Signal Process. 21 (2) (1999)
James E. Stine, Michael J. Schulte
A Combined Interval and Floating Point Multiplier. Great Lakes Symposium on VLSI (1998)
Michael J. Schulte, James E. Stine
Symmetric Bipartite Tables for Accurate Function Approximation. IEEE Symposium on Computer Arithmetic (1997)
Michael J. Schulte, James E. Stine
Accurate Function Approximations by Symmetric Table Lookup and Addition. ASAP (1997)