Samira Ataei

Publication Activity (10 Years)

Years Active: 2015-2021
Publications (10 Years): 12

Top Topics

Open Source Projects

Delay Insensitive

Asynchronous Circuits

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Embed. Syst. Lett.

Publications

Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali
An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test 38 (2) (2021)
Samira Ataei, Rajit Manohar
Shared-Staticizer for Area-Efficient Asynchronous Circuits. ASYNC (2020)
Samira Ataei, Rajit Manohar
AMC: An Asynchronous Memory Compiler. ASYNC (2019)
Samira Ataei, James E. Stine
A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. IEEE Embed. Syst. Lett. 10 (1) (2018)
Samira Ataei, James E. Stine
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. SoCC (2018)
Samira Ataei, Matthew Gaalswyk, James E. Stine
A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. MWSCAS (2017)
Rabin Thapa, Samira Ataei, James E. Stine
WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. MSE (2017)
Samira Ataei, James E. Stine
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. ACM Great Lakes Symposium on VLSI (2017)
Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar
OpenRAM: an open-source memory compiler. ICCAD (2016)
Samira Ataei, James E. Stine, Matthew R. Guthaus
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD (2016)
Samira Ataei, James E. Stine
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. ACM Great Lakes Symposium on VLSI (2015)
Samira Ataei, James E. Stine
A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. IGSC (2015)