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A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS.
Samira Ataei
James E. Stine
Matthew R. Guthaus
Published in:
ICCD (2016)
Keyphrases
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low voltage
cmos technology
random access memory
flip flops
design considerations
low power
silicon on insulator
power dissipation
power consumption
leakage current
high speed
power line
low cost
nm technology
parallel processing
image sensor
dynamic range
design process
e learning