E. George Walters III

Publication Activity (10 Years)

Years Active: 2003-2016
Publications (10 Years): 1

Top Topics

Hardware Implementation

Symmetric Matrix

Top Venues

Publications

E. George Walters III
Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs. Comput. 5 (4) (2016)
E. George Walters III
24-bit significand multiplier for FPGA floating-point multiplication. ACSSC (2015)
E. George Walters III
Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers. Comput. 4 (4) (2015)
E. George Walters III
Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs. ACSSC (2014)
Masoud Sadeghian, James E. Stine, E. George Walters III
Optimized cubic chebyshev interpolator for elementary function hardware implementations. ISCAS (2014)
E. George Walters III
FPGA-accelerated simulation of truncated-matrix multipliers. ACSCC (2012)
E. George Walters III, Michael J. Schulte
Truncated-matrix multipliers with coefficient shifting. ACSCC (2011)
E. George Walters III, Michael J. Schulte
Efficient Function Approximation Using Truncated Multipliers and Squarers. IEEE Symposium on Computer Arithmetic (2005)
Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner
Combined Multiplication and Sum-of-Squares Units. ASAP (2003)