Alberto Nannarelli

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 29

Top Topics

Hardware Implementation

Special Section

Multicore Processors

Top Venues

IEEE Trans. Computers

IEEE Trans. Emerg. Top. Comput.

Publications

David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek
Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers 73 (1) (2024)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re
Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC (2023)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò
An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access 11 (2023)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re
Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. 10 (1) (2022)
Stuart F. Oberman, Leonel Sousa, Bogdan Pasca, Alberto Nannarelli
Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Mioara Joldes, Fabrizio Lamberti, Alberto Nannarelli
Special Section on "Emerging and Impacting Trends on Computer Arithmetic". IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Hong-Ning Dai Senior, Zibin Zheng, Yan Zhang, Michael Rung-Tsong Lyu, Alberto Nannarelli
Special Section on Scalable Computing for Blockchain Systems. IEEE Trans. Emerg. Top. Comput. 9 (3) (2021)
Alberto Nannarelli
Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors. ARITH (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò
FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC (2019)
L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Digital Signal Processing Accelerator for RISC-V. ICECS (2019)
Alberto Nannarelli
Tunable Floating-Point Adder. IEEE Trans. Computers 68 (10) (2019)
Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò
A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access 7 (2019)
Alberto Nannarelli
Fused Multiply-Add for Variable Precision Floating-Point. SoCC (2019)
Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re
An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access 7 (2019)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD (2018)
Alberto Nannarelli
Tunable Floating-Point for Energy Efficient Accelerators. ARITH (2018)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC (2018)
Marta Franceschi, Alberto Nannarelli, Maurizio Valle
Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation. SMACD (2018)
Marta Franceschi, Alberto Nannarelli, Maurizio Valle
Tunable Floating-Point for Artificial Neural Networks. ICECS (2018)
Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari
Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC (2017)
Alberto Nannarelli
A multi-format floating-point multiplier for power-efficient operations. SoCC (2017)
Jonathan Taylor, Alberto Nannarelli
Design and simulation of a quaternary memory cell based on a physical memristor. NORCAS (2016)
Alberto Nannarelli
Performance/Power Space Exploration for Binary64 Division Units. IEEE Trans. Computers 65 (5) (2016)
Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
A hardware framework for on-chip FPGA acceleration. ISIC (2016)
A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC (2016)
Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems 39 (8) (2015)
Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Characterization of RNS multiply-add units for power efficient DSP. MWSCAS (2015)
Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re
A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT (2015)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC (2014)
Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 63 (8) (2014)
Alberto Nannarelli
Decimal engine for energy-efficient multicore processors. VLSI-SoC (2014)
Jakob Kenn Toft, Alberto Nannarelli
Energy efficient FPGA based hardware accelerators for financial applications. NORCHIP (2014)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC (2013)
Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Jonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli
Design of power efficient FPGA based hardware accelerators for financial applications. NORCHIP (2012)
Tomás Lang, Alberto Nannarelli
Comments on 'improving the speed of decimal division'. IET Comput. Digit. Tech. 6 (6) (2012)
Wei Liu, Alberto Nannarelli
Power Efficient Division and Square Root Unit. IEEE Trans. Computers 61 (8) (2012)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Imprecise arithmetic for low power image processing. ACSCC (2012)
Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Power efficient design of parallel/serial FIR filters in RNS. ACSCC (2012)
Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
Temperature dependent wire delay estimation in floorplanning. NORCHIP (2011)
Alberto Nannarelli
Radix-16 Combined Division and Square Root Unit. IEEE Symposium on Computer Arithmetic (2011)
Alberto Nannarelli
FPGA Based Acceleration of Decimal Operations. ReConFig (2011)
Nicolas Borup, Jonas Dindorp, Alberto Nannarelli
FPGA implementation of decimal processors for hardware acceleration. NORCHIP (2011)
Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino
Post-placement temperature reduction techniques. DATE (2010)
Wei Liu, Alberto Nannarelli
Power dissipation challenges in multicore floating-point units. ASAP (2010)
Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino
On-chip Thermal Modeling Based on SPICE Simulation. PATMOS (2009)
Tomás Lang, Alberto Nannarelli
Division Unit for Binary Integer Decimals. ASAP (2009)
Wei Liu, Alberto Nannarelli
Power dissipation in division. ACSCC (2008)
Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) (2008)
Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS (2008)
Luigi Dadda, Alberto Nannarelli
A variant of a radix-10 combinational multiplier. ISCAS (2008)
Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Reducing power dissipation in pipelined accumulators. ACSCC (2008)
Alberto Nannarelli
Session TP8b1: Computer arithmetic II. ACSCC (2008)
Tomás Lang, Alberto Nannarelli
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. IEEE Trans. Computers 56 (6) (2007)
G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power adaptive filter based on RNS components. ISCAS (2007)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers 54 (7) (2005)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic (2005)
Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) (2005)
Andrea Del Re, Alberto Nannarelli, Marco Re
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. DATE (2004)
Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) (2004)
Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re
Power-delay tradeoffs in residue number system. ISCAS (5) (2003)
Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Power characterization of digital filters implemented on FPGA. ISCAS (5) (2002)
Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP (2002)
Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono
FPGA realization of RNS to binary signed conversion architecture. ISCAS (4) (2001)
Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli
Tradeoffs between residue number system and traditional FIR filters. ISCAS (2) (2001)
Luca Benini, Alberto Macii, Alberto Nannarelli
Cached-code compression for energy minimization in embedded processors. ISLPED (2001)
Alberto Nannarelli, Tomás Lang
Low-Power Divider. IEEE Trans. Computers 48 (1) (1999)
Alberto Nannarelli, Tomás Lang
Low-Power Radix-4 Combined Division and Square Root. ICCD (1999)
Alberto Nannarelli, Tomás Lang
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. IEEE Symposium on Computer Arithmetic (1999)
Alberto Nannarelli, Tomás Lang
Power-delay tradeoffs for radix-4 and radix-8 dividers. ISLPED (1998)
Alberto Nannarelli, Tomás Lang
Low-power radix-8 divider. ICCD (1998)
Alberto Nannarelli, Tomás Lang
Low-power radix-4 divider. ISLPED (1996)