Marco Re

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 45

Top Venues

ApplePies

ACSSC

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Access

Publications

Lorenzo Canese, Gian Carlo Cardarilli, Riccardo La Cesa, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò
A Novel Digital Equalizer Based on RF Sampling Beyond GHz. IEEE Access 12 (2024)
Stefano Bertazzoni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey. IEEE Access 12 (2024)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re
Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC (2023)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò
An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access 11 (2023)
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò
Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. ACSSC (2023)
Damiano Angeloni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Sergio Spanò
A RISC-V Hardware Accelerator for Q-Learning Algorithm. ApplePies (2023)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re
Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. 10 (1) (2022)
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. ApplePies (2022)
D. Errico, Marco Re, V. Colombo, Gian Carlo Cardarilli, M. Martina, M. Ruo Roch
AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation. ApplePies (2022)
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Hamed Famil Ghadakchi, Marco Re, Sergio Spanò
Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance. Sensors 22 (22) (2022)
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
FPGA-Based Road Crack Detection Using Deep Learning. SYSINT (2022)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Andrea Ricci, Sergio Spanò
An FPGA-based multi-agent Reinforcement Learning timing synchronizer. Comput. Electr. Eng. 99 (2022)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Marco Re
Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT. SYSTEM (2021)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Matteo Guadagno, Marco Re, Sergio Spanò
A M-PSK Timing Recovery Loop Based on Q-Learning. ApplePies (2021)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Massimo Panella, Marco Re, Antonello Rosato, Sergio Spanò
A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Dario Natale, Marco Re, Sergio Spanò
"MR Q-Learning" Algorithm for Efficient Hardware Implementations. ACSCC (2021)
Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps. IEEE Trans. Circuits Syst. II Express Briefs (2) (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò
An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators. ApplePies (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò
FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC (2019)
L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Digital Signal Processing Accelerator for RISC-V. ICECS (2019)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò
Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning. ApplePies (2019)
Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò
A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access 7 (2019)
Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re
An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access 7 (2019)
Marco Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, Carla Andreani, Gian Carlo Cardarilli, Carlo Cazzaniga, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Pedro Reviriego, Gianluca Furano, Roberto Senesi
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility. DTIS (2018)
Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi
Hardware design of LIF with Latency neuron model with memristive STDP synapses. CoRR (2018)
Gian Carlo Cardarilli, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Lorenzo Simone, Sergio Spanò
Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming. ApplePies (2018)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD (2018)
Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò
IP Generator Tool for Efficient Hardware Acceleration of Self-organizing Maps. ApplePies (2018)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC (2018)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò
Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration. ApplePies (2018)
Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari
Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC (2017)
Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi
Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integr. 59 (2017)
Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò, Dario Gelfusa, Lorenzo Simone
Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR. ApplePies (2017)
Francesca Silvestri, Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Luca Di Nunzio, Rocco Fazzolari, Marco Re
FPGA Implementation of a Low-Power QRS Extractor. ApplePies (2017)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Luca Gerardi, Marco Re, Giovanni Campolo, Domenico Cascone
A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. ISCAS (2017)
Simone Acciarito, Daniele Giardino, Gaurav Mani Khanal, Marco Re, Francesca Silvestri, Sergio Spanò
FPGA Implementation of a Channelizer with 2048 Channels Utilizing USRP-SDR Platform for Satellite Communications. ApplePies (2017)
Filippo Giuliani, Marco Ottavi, Gian Carlo Cardarilli, Marco Re, Luca Di Nunzio, Rocco Fazzolari, Antimo Bruno, Francesco Zuliani
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. DFT (2016)
Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re
Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach. ApplePies (2016)
Gaurav Mani Khanal, Simone Acciarito, Gian Carlo Cardarilli, Abhishek Chakraborty, Luca Di Nunzio, Rocco Fazzolari, Alessandro Cristini, Gianluca Susi, Marco Re
ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior. ApplePies (2016)
Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
A hardware framework for on-chip FPGA acceleration. ISIC (2016)
A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC (2016)
Amirhossein Fereidountabar, Gian Carlo Cardarilli, Marco Re
High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates. J. Electr. Comput. Eng. 2015 (2015)
Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
A Wireless Sensor Node Based on Microbial Fuel Cell. ApplePies (2015)
Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Characterization of RNS multiply-add units for power efficient DSP. MWSCAS (2015)
Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re
A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT (2015)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC (2014)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
TDES cryptography algorithm acceleration using a reconfigurable functional unit. ICECS (2014)
Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Marco Re, Mario Salerno, Gianluca Susi
Spiking neural networks based on LIF with latency: Simulation and synchronization effects. ACSSC (2013)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC (2013)
Gian Carlo Cardarilli, Marco Re, Ilir Shuli
High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs. ApplePies (2013)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Salvatore Pontarelli, Marco Re
A Reconfigurable Functional Unit for Modular Operations. ApplePies (2013)
Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone
Compressive sensing spectrum analysis for space autonomous radio receivers. ACSSC (2013)
Pietro Albicocco, Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re
Karatsuba implementation of FIR filters. ACSCC (2012)
Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
Optimized Implementation of RNS FIR Filters Based on FPGAs. J. Signal Process. Syst. 67 (3) (2012)
Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
Imprecise arithmetic for low power image processing. ACSCC (2012)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Ruby B. Lee
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. ACSCC (2012)
Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Power efficient design of parallel/serial FIR filters in RNS. ACSCC (2012)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
Fine-grain Reconfigurable Functional Unit for embedded processors. ACSCC (2011)
Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone
Partial reconfiguration in the implementation of autonomous radio receivers for space. ReCoSoC (2011)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit. WISES (2010)
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Christian Lenci, Marco Re
VLSI implementation of reconfigurable cells for RFU in embedded processors. ICECS (2010)
Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
Error Correction Codes for SEU and SEFI Tolerant Memory Systems. DFT (2009)
Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
Error detection in addition chain based ECC Point Multiplication. IOLTS (2009)
Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
Speed-up of RISC Processor Computation using ADAPTO. ISCAS (2009)
Gian Carlo Cardarilli, Marco Re, Leonardo Di Carlo
Improved Large-signal Model for Vacuum Triodes. ISCAS (2009)
Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. ISCAS (2009)
Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
A Novel Error Detection and Correction Technique for RNS Based FIR Filters. DFT (2008)
Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) (2008)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs. ICECS (2008)
Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS (2008)
Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
Reducing power dissipation in pipelined accumulators. ACSCC (2008)
Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. ICECS (2008)
Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
Totally Fault Tolerant RNS Based FIR Filters. IOLTS (2008)
Francesco Iacomacci, Catherine Morlet, Francesca Autelitano, Gian Carlo Cardarilli, Marco Re, Enrico Petrongari, Gino Bogo, Mario Franceschelli
A Software Defined Radio Architecture for a Regenerative Onboard processor. AHS (2008)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Analysis of Errors and Erasures in Parity Sharing RS Codecs. IEEE Trans. Computers 56 (12) (2007)
Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS (2007)
G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power adaptive filter based on RNS components. ISCAS (2007)
Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT (2007)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Concurrent Error Detection in Reed-Solomon Encoders and Decoders. IEEE Trans. Very Large Scale Integr. Syst. 15 (7) (2007)
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. IEEE Trans. Computers 55 (5) (2006)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Fault tolerant design of signed digit based FIR filters. ISCAS (2006)
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Localization of Faults in Radix-n Signed Digit Adders. IOLTS (2006)
Gian Carlo Cardarilli, Andrea Del Re, Marco Re, Lorenzo Simone
Optimized QPSK modulator for DVB-S applications. ISCAS (2006)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Concurrent error detection in Reed Solomon decoders. ISCAS (2006)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Design of a Self Checking Reed Solomon Encoder. IOLTS (2005)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Self Checking Reed Solomon Encoder: Design and Analysis. DFT (2005)
Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
FPGA oriented design of parity sharing RS codecs. DFT (2005)
Gian Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Comparative Evaluation of Designs for Reliable Memory Systems. J. Electron. Test. 21 (4) (2005)
D. Bianchi, Gian Carlo Cardarilli, Andrea Del Re, A. Malatesta, Marco Re
FPGA implementation of a general purpose HMM processor based on token passing algorithm. ECCTD (2005)
Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) (2005)
Andrea Del Re, Alberto Nannarelli, Marco Re
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. DATE (2004)
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. DFT (2004)
Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. IOLTS (2004)
Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) (2004)
Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re
Power-delay tradeoffs in residue number system. ISCAS (5) (2003)
Gian Carlo Cardarilli, Andrea Del Re, Marco Re
IP based reconfigurable digital platform for satellite communications. ISCAS (2) (2003)

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Publication Activity (10 Years)

Top Topics

Top Venues

Marco Re